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Unformatted text preview: ECE/CS 352 Demo Section 602 Fall 2009 Experiment 3 Pre-demo Report Submitted by: Michael Frederick TA: Meng Shi Page 1 of 3 Description of Applied Homework I designed two main circuits. The first is a synchronous BCD counter with asynchronous reset and an enable input. The second circuit is a divide-by-N counter, where I added logic to force the counter to go to 0 at the desired count. I also studied the difference in time-based behavior between a latch and a flip-flop. Answers to Assignment Questions 1. Attachment F 2. Reducing logic would further simplify our design but it could also decrease the performance of our circuit. 3. The benefit of using a FF enable to control whether or not the counter increments is that the enable input permits individual BCD digit counters to be cascaded into multi- digit synchronous counters. The carry-in of the BCD-incrementer wouldn't give us this digit synchronous counters....
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This note was uploaded on 02/19/2010 for the course CS 252 taught by Professor Wood during the Fall '08 term at Wisconsin.
- Fall '08