hw2 - (a) F = A + B+ C+ D NOR4 (b) F = ABC+ DE AOI32 (c) G...

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ECE 3060 VLSI and Advanced Digital Design Homework 2 Homework must be submitted to Pam Halverson in KACB 2350 by 4:30 PM. 1. Wolf 2-1 2. Wolf 2-5 3. Consider a CMOS inverter with input voltage Gnd V in V DD . Identify which mode of operation (cutoff, linear, saturation) each FET is in as V in is varied across its range. 4. Design a complex gate cell (transistor schematic and stick diagram) for the fol- lowing functions. Use the parallel diffusion (Euler path) style of layout.
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Unformatted text preview: (a) F = A + B+ C+ D NOR4 (b) F = ABC+ DE AOI32 (c) G = (A + B+ C+ D)(E+ F) OAI42 (d) F = AB+ BC+ AC Majority 5. Design a cell (stick diagram) for the function in (d) using only NAND2, NAND3, and possibly inverters, such that (a) the cell is as short as possible (minimize vertical pitch between Vdd and Gnd) and the area is minimized. (b) the cell is as square as possible and the area is minimized. Fall 2007 Due: 10 September, 2007...
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This note was uploaded on 02/19/2010 for the course ECE 3060 taught by Professor Shimmel during the Spring '07 term at Georgia Institute of Technology.

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