# hw3 - 2. Calculate the worst-case RC delay of the following...

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ECE3060: VLSI and Advanced Digital Design Fall 2007 Homework #3: due September 17, 4:30pm 1. Consider the following Boolean function: F = ( a 0 + b )( c 0 + de 0 ) + f . (a) Draw the transistor-level schematic of the “complex gate implementation” of F . Assume that comple- mented inputs are available. (b) Assume that the width of the nFET for input a is 4x the minimum, i.e., w n ( a ) = 4 w min , determine the size of other FETs so that the worst-case rise and fall time are matched. (c) Draw the stick diagram of part a). (d) Draw the gate-level schematic of F using NAND2s and INVs only. Assume that complemented inputs are not available. (e) Using a single Vdd/Gnd rail, draw the stick diagram of the “network-of-gate implementation” of F . (hint: use the stick diagram of NAND2s and INVs and connect them as done in part d).
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Unformatted text preview: 2. Calculate the worst-case RC delay of the following complex gates in terms of τ . w p = 3 means that all pFETs have the width of 3 w min in the complex gate, where w min is the minimum FET width. Note that such sizings may cause unequal rise and fall times as well as unequal delays among the paths in the gate. For part (c) and (d), simplify F so that the minimum number of transistors is used. Assume that complemented inputs are available. (a) INV ( w p = 4 and w n = 4) driving a load of 4 C inv . (b) NAND4 ( w p = 10 and w n = 5) driving a load of 10 C inv . (c) F = ab + a c + bd ( w p = 5 and w n = 10) driving a load of 5 C inv . (d) F = a ⊕ ( b + a c ) ( w p = 5 and w n = 5) driving a load of 5 C inv ....
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## This note was uploaded on 02/19/2010 for the course ECE 3060 taught by Professor Shimmel during the Spring '07 term at Georgia Tech.

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