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Unformatted text preview: 2. Calculate the worstcase RC delay of the following complex gates in terms of τ . w p = 3 means that all pFETs have the width of 3 w min in the complex gate, where w min is the minimum FET width. Note that such sizings may cause unequal rise and fall times as well as unequal delays among the paths in the gate. For part (c) and (d), simplify F so that the minimum number of transistors is used. Assume that complemented inputs are available. (a) INV ( w p = 4 and w n = 4) driving a load of 4 C inv . (b) NAND4 ( w p = 10 and w n = 5) driving a load of 10 C inv . (c) F = ab + a c + bd ( w p = 5 and w n = 10) driving a load of 5 C inv . (d) F = a ⊕ ( b + a c ) ( w p = 5 and w n = 5) driving a load of 5 C inv ....
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This note was uploaded on 02/19/2010 for the course ECE 3060 taught by Professor Shimmel during the Spring '07 term at Georgia Tech.
 Spring '07
 Shimmel
 Gate, Transistor

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