hw4 - in to C out of a Carry select block is 40 ps....

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ECE 3060 VLSI and Advanced Digital Design Homework 4 Homework should be submitted in KACB 2350 by 4:30 PM on the due date. 1. Consider a bit slice consisting of a full adder and a function block. The full adder should take its operands from X i and Y i (and C i ), and if enabled, place its result on Z i . (and C i+1 ) The function block should compute any boolean function of X i and Y i and if enabled, place its result on Z i . (a) Design a transistor schematic for these modules. (b) Design the bit-slice at the stick diagram level. 2. Consider the design of a Carry-select adder. Suppose you have ripple-carry (or MCC) blocks that have a delay from C in to C out of 50 ps/bit. Further suppose that the multiplexing delay from C
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Unformatted text preview: in to C out of a Carry select block is 40 ps. Starting with a 4-bit block in the rst stage, design a 32 bit carry select adder at the block level (adder blocks and multiplexor blocks) which results in minimum delay. Be sure to show the width (in bits) of each block in your design, and also give the worst case delay to compute a valid sum. 3. Consider an (already designed) 4-bit barrel shifter as presented in lecture. (a) Show a design at the block level which enables the barrel shifter to shift ei-ther right or left. (b) Produce a oorplan for the module designed in (a). Fall 2007 Due: 24 September, 2007 Sections A,B,RPY...
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