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Unformatted text preview: in to C out of a Carry select block is 40 ps. Starting with a 4-bit block in the rst stage, design a 32 bit carry select adder at the block level (adder blocks and multiplexor blocks) which results in minimum delay. Be sure to show the width (in bits) of each block in your design, and also give the worst case delay to compute a valid sum. 3. Consider an (already designed) 4-bit barrel shifter as presented in lecture. (a) Show a design at the block level which enables the barrel shifter to shift ei-ther right or left. (b) Produce a oorplan for the module designed in (a). Fall 2007 Due: 24 September, 2007 Sections A,B,RPY...
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- Spring '07