hw5 - Fall 2007 Due: 17 October, 2007 Section A, B, RPY ECE...

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Unformatted text preview: Fall 2007 Due: 17 October, 2007 Section A, B, RPY ECE 3060 Homewo rk 5 VLSI an d Advance d Dig ital Design Homewo rk should be submitte d at KACB 3318 by 4:30 PM 1. We have seen in lecture that the delay of a gate w ith input capacitance Cin driving a load of Cout is d = gh + p = f + p . Show that f = RoutCout , where Rout is the worst case resistance of the pullup an d pulldown networks. 2. Calculate the logical effort g for the follow ing complex gates (show your work). Assume that the w idth of a pfet in an inverter is tw ice the w idth of an nfet in that inverter. (a) z = qrstuv (NAND6) z = q + r + s + t + u + v + w + x (NOR8) z = qrst + uvwx ( AOI44) z = (q + r + s)(t + u + v)(w + x + y) (OAI333) (b) (c) (d) 3. Repeat 2. assuming that the w idth of pfet an d the nfet in an inverter are identical. 4. Size the follow ing circuits an d calculate optimal delay using the metho d of LE assuming equal worst case rise an d fall time. Size the output gate in units of lamb da (assuming our design rules). All other gates may be size d in capacitance units. Homew2005 7 October 5, ork Due: Wednesday, 26 October, 2005 at 4:30PM in CCB 360 October 5, 2005 Due: Wednesday, 26 October, 2005 at 4:30PM in CCB 360 1. Resize the following circuits and calculate optimal delay using the method of LE assuming equal worst case rise and Call= Cinv an d Cout = 45Cinv . Repeat for Cout = 400Cinv . (a) Assume f in time. 1. (i) AssumeollowingC ircuits and calculate optimal delay Csing= he mC . of LE assuming Resize the f C = c and C u t 400 ethod in inv out = 45 C inv . Repeat for out inv equal worst case rise and fall time. (i) Assume C in = C inv and C out = 45 C inv . Repeat for C out = 400 C inv . C out C out (ii) Assume C in = C inv and C out = C inv . Repeat for C out = 250 C inv (b) Assume Cin = Cinv an d Cout = Cinv . Repeat for Cout = 250Cinv . (ii) Assume C in = C inv and C out = C inv . Repeat for C out = 250 C inv C out C out 2. Sketch a design for 6-64 decoder whose outputs must drive 500 C inv of load. You do not need to fully explore the design space. However, you should indicate how many levels of logietch u expect, for 6-64 tdiecoder enhose n utputs imk is dirivly500 t, and ofhly. Assumedto atot Sk c yo a design and wha mplem w tatio oyou th n ust l kee bes C inv w oad. You h n yneedado reslsy iexplarre drie en siy n snime.m siwe vnv, rtors,shnd lwonsticase hiow imaboultetveiceof our t d fu l l nes o e th v de b g mi pac u Ho z e i ere y e u a ou d i r d cat e r se s any w ls 5. For the follow ing circuit, calculate the branching effort which result in equal deasolongyas worst ct, anfall time mplementation you think thelikely best,inverter).y. Assume that case d w (min nfet pfet is prototype l gic laou for epaths frhat i a to sizean d and o y, in ssuming the and whcapacitance at a is Cinv. y exp om x, at a input your address lines are driven by minimum size inverters, and worst case rise is about twice as long as worst case fall time (min size nfet and pfet in the prototype inverter). x Cx 2. a y Cy (a) (b) Assuming Cx = Cy = 10Cinv Assuming Cx = 2Cinv an d Cy = 10Cinv 6. Repeat 5 to minimize the delay from a to y. ...
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