# hw6 - I 1 to O 2 and nd C in for all gates along the path....

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ECE3060: VLSI and Advanced Digital Design Fall 2007 Homework #6: due Oct 23, 4:30pm For all problems below, the output polarity should be unchaged when an ideal number of stage is used. Use ρ = 4 for determining the ideal number of stage. Note that for Problem 2 and 3 it is possible for some transistors to have smaller width than the minimum allowed. 1. Consider the complex gate implementation of F = (¯ a + ¯ b c + ¯ d . (a) Compute the logical eﬀort of F for input a . (b) Using input a , compute the minimum delay if F is driving a load of 20 C inv (ideal number of stage is required). Assume that C in for a is 2 C inv , and the parasitic delay of F is 4. 2. Consider the following Boolean network. Assume that the load at all inputs is C inv , and the load at all outputs is 100 C inv . Use fanout for branching factor computation. I 1 F I 2 I 3 O 1 O 2 g7 g1 g2 g3 g4 g5 g6 g8 (a) Compute the minimum delay from
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Unformatted text preview: I 1 to O 2 and nd C in for all gates along the path. Ideal number of stages is not required. (b) Repeat part (a) so that the ideal number of stages is used. Which case results in smaller delay? (c) Compute the width of the transistors from part (b) in terms of . Assume that the minimum width of nFET is 0 . 27 . 3. We are trying to minimize the delay from I 3 to O 1 , where I 3 is connected to the input a of F from Problem 1. (a) Using the sizing results from Problem 2(a), compute the minimum delay from I 3 to g 7 and nd C in for all gates along the path (ideal number of stages is not required). (b) Using the sizing results from Problem 2(a), compute the minimum delay from g 4 to O 1 and nd C in for all gates along the path (ideal number of stages is required)....
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## This note was uploaded on 02/19/2010 for the course ECE 3060 taught by Professor Shimmel during the Spring '07 term at Georgia Institute of Technology.

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