This preview shows page 1. Sign up to view the full content.
Unformatted text preview: I 1 to O 2 and nd C in for all gates along the path. Ideal number of stages is not required. (b) Repeat part (a) so that the ideal number of stages is used. Which case results in smaller delay? (c) Compute the width of the transistors from part (b) in terms of . Assume that the minimum width of nFET is 0 . 27 . 3. We are trying to minimize the delay from I 3 to O 1 , where I 3 is connected to the input a of F from Problem 1. (a) Using the sizing results from Problem 2(a), compute the minimum delay from I 3 to g 7 and nd C in for all gates along the path (ideal number of stages is not required). (b) Using the sizing results from Problem 2(a), compute the minimum delay from g 4 to O 1 and nd C in for all gates along the path (ideal number of stages is required)....
View
Full
Document
This note was uploaded on 02/19/2010 for the course ECE 3060 taught by Professor Shimmel during the Spring '07 term at Georgia Institute of Technology.
 Spring '07
 Shimmel

Click to edit the document details