hw10sol - ECE 3060 VLSI and Advanced Digital Design...

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Unformatted text preview: ECE 3060 VLSI and Advanced Digital Design Homework 10 1.Consider a standard cell library consisting of the following cells: Cell Area Delay Input load INV 3 1+l 1 SINV2 6 1+0.5l 2 SINV4 10 1+0.25l 4 NOR2 7 2+2l 2 NAND2 5 2+1.5l 1 OAI21 7 3+2l 2 Fall 2007 Due: 7 December, 2007 Section A, B, RPY (i) Using INV and NAND2 as base function, draw pattern trees of the cells in the library. (ii) Using INV and NAND2 as base function, draw the subject tree of . (iii) Find a minimum area mapping of f. (Vertex taken from part ii.) Vertex Match Gate Cost X8 t2 Nand2(a,b) 5 X9 t1 Inv(c) 3 X10 t1 Inv(d) 3 X11 t2 Nand2(b,e) 5 X12 t1 Inv(a) 3 X13 t1 Inv(c) 3 X4 t1 Inv(X8) 8 t1 Sinv2(X8) 11 t1 Sinv4(X8) 15 X5 t2 Nand2(X9,X10) 11 X6 t1 Inv(X11) 8 t1 Sinv2(X11) 11 t1 Sinv4(X11) 15 X7 t2 Nand2(X12,X13) 11 X2 t2 Nand2(X4,X5) 24 t4 OAI21(X9,X10,X4) 21 X3 t2 Nand2(X6,X7) 24 t4 OAI21(X12,X13,X6) 21 X1 t2 Nand2(X2,X3) 47 f =ab(c + d)+be(a +c) a b c d b e a c X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 (iv)...
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hw10sol - ECE 3060 VLSI and Advanced Digital Design...

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