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Unformatted text preview: transistors. ECE3060A Fall 2006, Midterm 1 3 2. (30pts) Consider the complex gate implementation of F = a ¯ b ⊕ a + c that uses the minimum number of transistors. Assume that complemented inputs are available. a) (15pts) Compute the worstcase RC delay of F driving a load of 5 C inv . Assume that the size of all transistors is ﬁxed to 1. b) (15pts) Compute the LE (logical eﬀort) delay of F driving a load of 5 C inv . Use input b , and assume that C in ( b ) = 2 C inv . The parasitic delay of F is 4. ECE3060A Fall 2006, Midterm 1 4 3. (40pts) Consider the following circuit. a b c d F a) (20pts) Draw the stick diagram of the complex gate implementation of F . Assume that complemented inputs are available. b) (20pts) Draw the stick diagram of the network of gate implementation of F . Use the gates given in the circuit. ECE3060A Fall 2006, Midterm 1 5 blank page...
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 Spring '07
 Shimmel
 ECE3060A Fall, School of Electrical and Computer Engineering Georgia Institute of Technology

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