Hw2soln - ECE 3060 VLSI and Advanced Digital Design Homework 2 Solution 1 Wolf 21 2 Wolf 22 Table 1 Ids neglectiing channel length modulation Vds

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ECE 3060 VLSI and Advanced Digital Design Homework 2 Solution September 20, 2002 1. Wolf 2–1 2. Wolf 2–2 3. Wolf 2–5 a) poly-poly spacing is due to process resolution limits. That is to say, smaller spacng would lead to unacceptable rate of poly-poly bridging faults (shorts). b) poly and metal do not interact. c)Registration error of in diffusion cut or metal in any direction still gives functional contact. d)Registration error of in diffusion and poly still gives functional transistor 4. For each of the following functions, design static CMOS transistor level designs. Be sure to indicate any necessary inverters: Table 1: Ids neglectiing channel length modulation Vds W/L 1 2 3.3 5 2.5 383.25 584 616.85 616.85 4 613.2 934.4 986.96 986.96 6 919.8 1401.6 1480.44 1480.44 12.5 1916.25 2920 3084.25 3084.25 2 λ 1 λ 1 λ
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(i) and (ii) and (iii) AB C D + () fA B C D + ABC D ++ == B C D + = Vdd A D C B f AB + CD + B + + + B + + =
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and 5. For each of the functions in question 4, use the parallel diffusion style of layout (stick dia- gram view) to design a cell to implement the function. Be sure to indicate the Euler path, and draw a stick diagram for the layout. Any necessary inverters should be included in the cell,
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This note was uploaded on 02/19/2010 for the course ECE 3060 taught by Professor Shimmel during the Spring '07 term at Georgia Institute of Technology.

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Hw2soln - ECE 3060 VLSI and Advanced Digital Design Homework 2 Solution 1 Wolf 21 2 Wolf 22 Table 1 Ids neglectiing channel length modulation Vds

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