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Unformatted text preview: ECE 3060
VLSI and Advanced Digital Design Test II . November 1 1 , 2002 This exam is closed book and no programmable calculators. You may have two sheet of notes
(both sides). There are three questions. Do read them over before you start to work, If you need to
make any assumptions, state them. The meaning of each question should be clear, but if some
thing does not make any sense to you, please ask for clariﬁcation. Good Luck! Name 3; (V no W1 l. (35) Consider the two input exclusive or function f = a G) b. Suppose a and b are driven
from minimum size inverters with input capacitance C m , and the function must drive a
load of 340 C in with minimum delay. a. (10) Assuming y = 2,what is the ideal number of levels of logic for this case?
7" 7 a F + 3‘ 6
9"“? H is £6.72 Weed chm Ctrccvf euﬂq (W 6 V a 6,}w A. ,__ 340 CIAV 10 (P):
— Lg : \ 23.5
75712 5 ' 7 > H 39’0 F= L208, 3 ﬁ=tﬁom4(s$4)=é A
5< )< é b. (10) Draw your circuit and indicate gate sizing (input capacitance of the gate sufﬁce c. (10) What is the delay through this circuit? (1. (5) Dfaw the Circuit that you would have chosen (to minimize delay) if the output load
were lCinv. [$4472 {5W H) rm” ("4) f. =¢L4 2‘0 2. (30) Logic Minimization
a. (15) Find the kernel set K(g) for the function g = ade + af + bde + bf. ﬂ/4 5 (124.15. cube in» ‘2, 4+; nee/{2419M m) c Mb» MW»? b. (15) Use BDDs and the method of determining single implicant containment presented in Class to ﬁnd if the implicant bcd is contained in the function f = aba’ + Etc . I— c, 3. Suppose you are given a standard cell library, with four gates: NAND, AND OAI21, and
INV. The area cost is given for each gate. a. (15) Draw the pattern trees for each cell in the library using base functions NANDZ and
INV. b. (20) Use the dynamic programming method for technology mapping, to map the circuit
shown.. (a ...
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 Spring '07
 Shimmel

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