{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

hw2 - Be sure to indicate all possible Euler paths for part...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
ECE3060 August 30 , 2006 Homework #2 Due Thursday August 31 @ 4:30pm 100 points 1. For the following functions, please design static CMOS transistor level complex gates. Please note that only a,b,c and d are available as inputs (complemented versions are not available). Be sure to draw any necessary inverters. a. a b c (Changed to 3-input XOR instead of 4-input XOR. Also you do not need to use the minimum number of transistors for this gate.) b. ( (a b) + ( c d ) ) (Use the smallest number of transistors possible for this gate.) 2. For each function in question 1, use the parallel diffusion style of layout to design a cell to implement the function.
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Be sure to indicate all possible Euler paths for part b (however you only need to indicate one Euler path for part a) and draw a (color) stick diagram for each layout. Any necessary inverters should be included in the cell, but not necessarily in the contiguous piece of diffusion. 3. Redraw the complex gates used in your answer to question 1 (do not redraw any inverters used). Obviously, you should have two CMOS complex gates (two pull-up/pull-down transistor networks). Size all transistors so that rise and fall times are matched. (note: the two gates do not have to have equal timing with respect to each other.)...
View Full Document

{[ snackBarMessage ]}

Ask a homework question - tutors are online