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hw3 - = a b c d(a Draw the transistor-level schematic of...

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ECE3060: VLSI and Advanced Digital Design Fall 2006 Homework #3: due September 7, 4:30pm, Total=100pts 1. Consider the following Boolean function: F = a ( b + cd )( e + f ). (a) Draw the transistor-level schematic of the “complex gate implementation” of F . (hint: complex gate implementation contains a single pair of pull-up and pull-down networks). Assume that complemented inputs are available. (b) Assuming w n a ) = 2 w min , where w n a ) denotes the width of the nFET for ¯ a , and w min denotes the minimum width of nFET, determine the size of other FETs so that the rise and fall time are matched. (c) Repeat part b) when w p ( ¯ b ) = 3 w min . 2. Consider the following Boolean function:
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Unformatted text preview: = ( a + b )( c + d ). (a) Draw the transistor-level schematic of the complex gate implementation of F . Assume that comple-mented inputs are available. (b) Size the transistors in part a) so that the rise and fall time are matched. Assume w n (¯ a ) = 4 w min . (c) Draw the stick diagram of part a). (d) Draw the gate-level schematic of F using NAND2s and INVs only. Assume that complemented inputs are not available. (e) Using a single Vdd/Gnd rail, draw the stick diagram of the “network-of-gate implementation” of F . (hint: use the stick diagram of NAND2s and INVs and connect them as in part d))....
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