hw4 - ECE3060 Homework#4 Due Thursday September 14 4:30pm...

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ECE3060 September 7, 2006 Homework #4 Due Thursday September 14 @ 4:30pm 100 pts. Please note that NO LATES will be accepted due to this homework being immediately necessary for lab3; i.e., solutions will be posted very soon after the due time in order to provide uniform answers for use in lab3. 1. (10) Design a truth table for a subtracter taking as input a 1-bit value A[0] and a 1-bit value B[0] where each input bit is unsigned. Assume that the output is a 2-bit value C[1:0] in two’s complement (i.e., 00 = 0, 01 = 1, 11 = -1, 10 = -2). Hint: it may be the case that not all outputs (two-bit two’s complement values) appear in the truth table. 2. (15) Given the truth table in your answer to (1.) above, design logic gates to implement the 1-bit subtracter. Show as inputs A[0] and B[0]; show as outputs C[1:0] = C[1], C[0]. Use as few logic gates as possible; feel free to design new complex gates as desired/needed (i.e., you are not limited to NAND, NOR and INV but instead may create new complex gates specific to this problem). 3. (15) Design a truth table for an adder that takes in two 2-bit inputs A[1:0] and B[1:0] in
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This note was uploaded on 02/19/2010 for the course ECE 3060 taught by Professor Shimmel during the Spring '07 term at Georgia Tech.

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