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Unformatted text preview: the gate. For part (c) and (d), simplify F so that the minimum number of transistors is used. Assume that complemented inputs are available. (a) INV ( w p = 3 and w n = 4) driving a load of 5 C inv . (b) NOR4 ( w p = 10 and w n = 5) driving a load of 10 C inv . (c) F = a ( b + c ) ( w p = 5 and w n = 10) driving a load of 5 C inv . (d) F = a ( b + ac ) ( w p = 5 and w n = 5) driving a load of C inv . 3. Consider the complex gate implementation of F = a ( b + c ) + d . (a) Draw the stick diagram. (b) Compute the total logical eort (= g tot ) and the input logical eort for a (= g a ). (c) Using input a and logical eort method, compute the delay when F is driving a load of 20 C inv . Assume that C in for a is 2 C inv , and the parasitic delay of F is 4....
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This note was uploaded on 02/19/2010 for the course ECE 3060 taught by Professor Shimmel during the Spring '07 term at Georgia Institute of Technology.
 Spring '07
 Shimmel

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