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hw5 - the gate For part(c and(d simplify F so that the...

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ECE3060: VLSI and Advanced Digital Design Fall 2006 Homework #5: due September 21, 4:30pm, Total=100pts Please note that late submission will not be accepted for this homework. 1. We are designing a 4-bit logical left barrel shifter. Assume that a 2-bit control signal d [0 , 3] specifies the shifting distance ( d 1 is MSB and d 0 is LSB). (a) Draw the stick diagram of a 2 × 1 MUX using transmission gates and INVs only. Use a single Vdd/Gnd rail. (b) Design the shifter using the MUX in part (a). You may use black boxes for the MUXs. Clearly mark all the IOs. 2. Calculate the worst case RC delay of the following complex gates in terms of τ . w p = 3 means that all pFETs have the width of 3 w min in the complex gate, where w min is the minimum FET width. Note that such sizings may cause unequal rise and fall times as well as unequal delays among the paths in
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Unformatted text preview: the gate. For part (c) and (d), simplify F so that the minimum number of transistors is used. Assume that complemented inputs are available. (a) INV ( w p = 3 and w n = 4) driving a load of 5 C inv . (b) NOR4 ( w p = 10 and w n = 5) driving a load of 10 C inv . (c) F = a ( b + c ) ( w p = 5 and w n = 10) driving a load of 5 C inv . (d) F = a ⊕ ( b + ac ) ( w p = 5 and w n = 5) driving a load of C inv . 3. Consider the complex gate implementation of F = a ( b + c ) + d . (a) Draw the stick diagram. (b) Compute the total logical eﬀort (= g tot ) and the input logical eﬀort for a (= g a ). (c) Using input a and logical eﬀort method, compute the delay when F is driving a load of 20 C inv . Assume that C in for a is 2 C inv , and the parasitic delay of F is 4....
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