hw6 - ECE3060 Homework #6 Due Thursday October 5 @ 4:30pm...

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ECE3060 September 28, 2006 Homework #6 Due Thursday October 5 @ 4:30pm 100 pts. For the following questions, assume the design of an ANDXOR gate where ANDXOR(a,b,c) = a(b c). The transistor network for this CMOS gate is as follows: 1. (35) Consider the following multi-stage logic network. Assume that for every input (s, t, u, v, w, x, y) Cin = 2Cinv. The output load for each output is shown (50Cinv). For branching computation, use fanout. a. (5) Calculate F = GBH for each possible path between input u and output g. b. (30) For the path with the largest F in your answer to (1.a), use the method of logical effort to resize the gates on the path to minimize delay. For each gate resized, it is sufficient to give the resulting input capacitance after resizing. Give the final delay found in terms of τ (Tau). (Note: although the ANDXOR gate was not used in problem 1 above, it will be used on the next problem on the next page.)
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2. (25) This problem involves determining exact transistor widths to achieve a given
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This note was uploaded on 02/19/2010 for the course ECE 3060 taught by Professor Shimmel during the Spring '07 term at Georgia Tech.

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hw6 - ECE3060 Homework #6 Due Thursday October 5 @ 4:30pm...

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