hw6_soln

# hw6_soln - ECE3060 Homework#6 Solutions 1(35 Consider the...

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ECE3060 October 2, 2006 Homework #6 Solutions 100 pts. 1. (35) Consider the following multi-stage logic network. Assume that for every input (s, t, u, v, w, x, y) Cin = 2Cinv. The output load for each output is shown (50Cinv). For branching computation, use fanout. a. (5) Calculate F = GBH for each possible path between input u and output g. Two Possible Paths: Path 1: u, b, d, g Total Logical Effort, G, is product of logical effort of each gate along path: Logical effort of 2-input NOR: g NOR2 = 5 3 , Logical effort of 2-input NAND: g NAND2 = 4 3 G = 0 5 3 \$ 4 3 \$ 5 3 1 Total branching effort, B, is product of branching effort for each gate along path: Fan-out of gate 2 is 2 Fan-out of gate 4 is 2 B = (2 \$ 2) Total Electrical Effort, H, is final load capacitance / input capacitance: H = Cout Cin = 0 50 Cinv 2 Cinv 1 = 25

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F = G \$ B \$ H = 0 5 3 \$ 4 3 \$ 5 3 1 \$ (2 \$ 2) \$ 0 50 Cinv 2 Cinv 1 F = 10000 27 Path 2: u, b, e, g G = 0 5 3 \$ 5 3 \$ 5 3 1 Fan-out of gate 5 is also 2, so: B = (2 \$ 2) (Same Total Electrical Effort H.) F = 0 5 3 \$ 5 3 \$ 5 3 1 \$ (2 \$ 2) \$ 0 50 2 1 F = 12500 27
b. (30) For the path with the largest F in your answer to (1.a), use the method of logical effort to resize the gates on the path to minimize delay. For each gate resized, it is sufficient to give the resulting input capacitance after resizing. Give the final delay

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hw6_soln - ECE3060 Homework#6 Solutions 1(35 Consider the...

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