hw7_soln

# hw7_soln - ECE3060: VLSI and Advanced Digital Design Fall...

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ECE3060: VLSI and Advanced Digital Design Fall 2006 Homework #7: due Oct 12, 4:30pm, total = 100pts Solutions 1. Consider the complex gate implementation of F = (a’ + b’)c’ + d’. (a) Draw the stick diagram of F. -5 incorrect stick diagram (b) Compute the logical effort of F for input a. g a = (Cin a ) / (Cinv) = (4+4) / 3 = 8/3 -5 incorrect g a

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(c) Using input a, compute the minimum delay if F is driving a load of 20Cinv (ideal number of stage is required). Assume that Cin for a is 2Cinv, and the parasitic delay of F is 4. F = GBH = 0 8 3 1 \$ (1) \$ 0 20 Cinv 2 Cinv 1 = 80 3 N = ln 0 80 3 1 ln(4) = 2.368 / 3 f = F 1 N = 0 80 3 1 1 3 = 2.368 Delay = N \$ f C P = 3 \$ 2.368 C (4 C 1 C 1) = 14.96 t -5 did not use ideal # of stages -5 no delay calculation -2.5 incorrect parasitics: remember p inv = 1 -2.5 incorrect logical effort: remember logical effort is on a per-input basis -2.5 did not use the “complex gate implementation” of F 2. Consider the following Boolean network. Assume that the load at all inputs is C inv , and the load at all outputs is 100C inv . Use fanout for branching factor computation.
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## This note was uploaded on 02/19/2010 for the course ECE 3060 taught by Professor Shimmel during the Spring '07 term at Georgia Tech.

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hw7_soln - ECE3060: VLSI and Advanced Digital Design Fall...

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