sample1-lim - ECE3060 VLSI and Advanced Digital Design...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
ECE3060: VLSI and Advanced Digital Design Spring 2006, Prof. Sung Kyu Lim Midterm 1: February 17, 2006 Guidelines: 1. Read the questions carefully and pay attention to the special instructions. 2. Show all your work to receive the full credit. 3. State any assumptions you make on your solution. 4. Time: 11:05 - 11:55pm (50 min) 5. Total number of pages in this exam: 4 Name: Prob 1 (30 pts) Prob 2 (40 pts) Prob 3 (30 pts) TOTAL (100 pts) School of Electrical and Computer Engineering Georgia Institute of Technology
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
ECE3060 Spring’06, Midterm 1 2 1. (30pts) Choose either A or B from [A/B]. a) (7pts) In a pMOS transistor, we tie the n-well to [Vdd/Gnd] and apply a [negative/positive] V gs . This draws [electrons/holes] into the region below the gate, which in turn results in the channel changing to [p-type/n-type]. A [negative/positive] V ds sweeps [electrons/holes] from the source through the channel to drain, creating a [negative/positive] I ds . b) (4pts) In an inverter layout, the source terminal of pMOS is connected to [Vdd/Gnd], and
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 02/19/2010 for the course ECE 3060 taught by Professor Shimmel during the Spring '07 term at Georgia Tech.

Page1 / 4

sample1-lim - ECE3060 VLSI and Advanced Digital Design...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online