271hw3_sol - SAN JOSE STATE UNIVERSITY Charles W Davidson College of Engineering DEPARTMENT OF ELECTRICAL ENGINEERING EE271 Homework#3 Solution

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SAN JOSE STATE UNIVERSITY Charles W. Davidson College of Engineering DEPARTMENT OF ELECTRICAL ENGINEERING EE271 Homework #3 Solution Problem 1 module tr_latch (q_out, enable, data); output q_out; input enable, data; reg q_out; always @ (enable or data) begin if (enable) q_out = data; end endmodule module t_tr_latch (); wire q_out; reg enable, data; tr_latch M0 (q_out, enable, data); initial fork #3 data = 0; #5 forever #2 data = ~data; #30 data = 0; join initial fork #10 enable = 0; #20 enable = 1; #40 enable = 0; join initial #100 $finish; endmodule Problem 2 module Problem_3_2 (Y1, Y2, A, B, C, D); output Y1, Y2; input A, B, C, D; not (A_not, A); not (B_not, B); not (C_not, C); not (D_not, D); and (w4, A_not, B, C_not, D_not); and (w5, A_not, B, C_not, D); and (w6, A_not, B, C, D_not);
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and (w7, A_not, B, C, D); and (w11, A, B_not, C, D); and (w12, A, B, C_not, D_not); and (w13, A, B, C_not, D); or (Y1, w4, w5, w6, w7, w11, w12, w13); and (w1, A_not, B_not, C_not, D); and (w2, A_not, B_not, C, D_not); or (Y2, w1, w2, w4, w5); endmodule module t_Problem_3_2(); reg A, B, C, D; wire Y1, Y2; Problem_1 M0 (Y1, Y2, A, B, C, D); initial begin #5 {A, B, C, D} = 4'b0000; #5 {A, B, C, D} = 4'b0001; #5 {A, B, C, D} = 4'b0010; #5 {A, B, C, D} = 4'b0011; #5 {A, B, C, D} = 4'b0100; #5 {A, B, C, D} = 4'b0101; #5 {A, B, C, D} = 4'b0110; #5 {A, B, C, D} = 4'b0111; #5 {A, B, C, D} = 4'b1000; #5 {A, B, C, D} = 4'b1001; #5 {A, B, C, D} = 4'b1010; #5 {A, B, C, D} = 4'b1011; #5 {A, B, C, D} = 4'b1100; #5 {A, B, C, D} = 4'b1101; #5 {A, B, C, D} = 4'b1110; #5 {A, B, C, D} = 4'b1111; end initial begin #100 $finish; end endmodule T1 T2 Tdelta Name S 0 20 40 60 80 10 Default A B C D Y1 Y2
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Problem 3 For this problem, a testbench was developed to verify a gate-level model of a full adder. Since this is a 1-bit full adder, it was possible to test the module using every combination of inputs: a, b, and c_in. The expected results for each input combination are listed in the following table: a b c_in sum c_out 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 module Add_full(sum, c_out, a, b, c_in); output sum, c_out; input a, b, c_in; wire w1, w2, w3; Add_half M1(w1, w2, a, b); Add_half M2(sum, w3, w1, c_in); or #1 M3(c_out, w2, w3); endmodule module Add_half(sum, c_out, a, b); output sum, c_out; input a,b; xor #1 M1(sum, a, b); and #1 M2(c_out, a, b); endmodule module t_Adder(); wire sum, c_out; reg a, b, c_in; Add_full M0(sum, c_out, a, b, c_in); initial $monitor($time,,"a=%b, b=%b, c_in=%b, sum=%b, c_out=%b", a, b,
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This note was uploaded on 02/21/2010 for the course EE 271 taught by Professor Thuyle during the Spring '08 term at San Jose State University .

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271hw3_sol - SAN JOSE STATE UNIVERSITY Charles W Davidson College of Engineering DEPARTMENT OF ELECTRICAL ENGINEERING EE271 Homework#3 Solution

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