# 271hw4 - SAN JOSE STATE UNIVERSITY Charles W Davidson...

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1 of 2 SAN JOSE STATE UNIVERSITY Charles W. Davidson College of Engineering DEPARTMENT OF ELECTRICAL ENGINEERING EE271 Homework #4 1. For the circuit () YA D D B C =+ a. Write a gate-level Verilog code and its testbench. b. Write a Verilog code with user defined primitives (UDP) and its testbench. 2. Write a test bench to simulate a 16-bit Ripple Carry Adder as coded below ± Simulate the Verilog model and get the waveforms ± Turn in your HW with the printings of your source, testbench, and the output test waveforms. module Add_rca (sum, c_out, a, b, c_in); output [15:0] sum; output c_out; input [15:0] a, b; input c_in; wire c_in4, c_in8, c_in12, c_out; Add_rca_4 M1 (sum[3:0], c_in4, a[3:0], b[3:0], c_in); Add_rca_4 M2 (sum[7:4], c_in8, a[7:4], b[7:4], c_in4); Add_rca_4 M3 (sum[11:8], c_in12, a[11:8], b[11:8], c_in8); Add_rca_4 M4 (sum[15:12], c_out, a[15:12], b[15:12], c_in12); endmodule module Add_rca_4 (sum, c_out, a, b, c_in); output [3: 0] sum; output c_out; input [3: 0] a, b; input c_in; wire c_in2, c_in3, c_in4; Add_full M1 (sum[0], c_in2, a[0], b[0], c_in);

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271hw4 - SAN JOSE STATE UNIVERSITY Charles W Davidson...

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