271hw5 - Show the circuit 2 For a Verilog module and it’s...

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SAN JOSE STATE UNIVERSITY Charles W. Davidson College of Engineering DEPARTMENT OF ELECTRICAL ENGINEERING EE271 Homework #5 1. A circuit represented by Boolean equation below: ((A AND B) OR (A AND C)) OR (B AND C) a. If all gates are 2-input gates: show the circuit. How many levels? b. Optimize the circuit for area by just examine the Boolean equation. If all gates are 2-input gates: Show the optimized Boolean equation and the circuit. How many levels? c. If the user synthesize the circuit with a library that has only 2-input NAND gates, show the circuit d. If the user constraint to 2 levels and the library has only NAND gates with 2 or 3 inputs.
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Unformatted text preview: Show the circuit 2. For a Verilog module and it’s test wave forms below. Write a testbench to reproduce the same waveforms module HW5_Q2 (Y, A, B, C, D); output Y; input A, B, C, D; assign Y = (~(A | D)) & (B & C & ~D); endmodule T1 20 T2 Tdelta Name S 20 40 60 80 Default A B C D Y 3. Rewrite the Verilog module in question 2 above by using only Verilog primitives 4. Rewrite the Verilog module in question 2 above by using only one UDP. The module is shown as below, show your UDP module HW5_Q4 (Y, A, B, C, D); output Y; input A, B, C, D; HW5_Q4_UDP M0 (Y, A, B, C, D); endmodule...
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