271hw6 - SAN JOSE STATE UNIVERSITY Charles W. Davidson...

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SAN JOSE STATE UNIVERSITY Charles W. Davidson College of Engineering DEPARTMENT OF ELECTRICAL ENGINEERING EE271 Homework #6 Create a directory named “ HW6 ” and a subdirectory “ src ” on your UNIX account. Write a Verilog module for a16-bit ripple carry adder (combinational circuit) and a testbench to test the module. Save your Verilog source code in the “ src ” subdirectory. Complete the tasks below: 1. Use VCS to simulate your design module with your testbench and show the waveform 2. Rename your current .synopsys_dc.setup file to some other name so that you can save it. Make a new .synopsys_dc.setup file as shown below: set search_path {/apps/synopsys/SYNTH/libraries/syn \ /apps/synopsys/CORE/libraries/syn ./src} set link_library {* class.db and_or.db dw_foundation.sldb} set target_library {class.db and_or.db} set symbol_library {class.sdb generic.sdb} set synthetic_library {dw_foundation.sldb standard.sldb} Follow the steps below to synthesize your design (with Design Compiler in command mode):
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This note was uploaded on 02/21/2010 for the course EE 271 taught by Professor Thuyle during the Spring '08 term at San Jose State University .

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271hw6 - SAN JOSE STATE UNIVERSITY Charles W. Davidson...

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