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SAN JOSE STATE UNIVERSITY Charles W. Davidson College of Engineering DEPARTMENT OF ELECTRICAL ENGINEERING EE271 Homework #7 1. An addition circuit running at 100MHz with a supply voltage of 3V. Assume that on the average each node change states (from 0 to 1 or from 1 to 0) 2 times per 10 clock cycles and the total internal node capacitance is 10fF. Find the power consumption in the adder. 2. Modify the Verilog code below to improve the power consumption. Assume that signal enable is active (high) 20% of the time. Assume the adder consumes too little power that it is not worth to consider it for power optimization.
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This note was uploaded on 02/21/2010 for the course EE 271 taught by Professor Thuyle during the Spring '08 term at San Jose State University .
- Spring '08