271hw9 - SAN JOSE STATE UNIVERSITY Charles W. Davidson...

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SAN JOSE STATE UNIVERSITY Charles W. Davidson College of Engineering DEPARTMENT OF ELECTRICAL ENGINEERING EE271 Homework #9 1. For the 3 memory module below (may not work because they are not yet tested) Develop test benches to test them and correct the modules to make them work correctly. Synthesis the 3 designs with any constraint and attributes that are reasonable to you Turn in the corrected modules, test benches, simulation waveforms, and the synthesized circuits a. 16 x 8-bit Asynchronous SRAM `define DELAY 1 module Ram (data, address, memw, memr, cs); parameter width = 8, nbytes = 16, addr = 4; input memw, memr, cs; input [addr-1:0] address; inout [width-1:0] data; reg [width-1:0] mem [nbytes-1:0]; assign #`DELAY data = (cs & memr)?8'bz: mem[address]; always @(posedge memw) begin if(cs) mem[address] = data; end endmodule b. Verilog Coding of 16 x 8-bit Dual- Port Synchronous SRAM Can be written and read simultaneously Has 2 unidirectional data ports: an input and an output ports Each port has its own address buses
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271hw9 - SAN JOSE STATE UNIVERSITY Charles W. Davidson...

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