271s09_HW9_Q1_Sol

271s09_HW9_Q1_Sol - SOLUTION FOR QUESTION 1 OF HW #9 1. 16...

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SOLUTION FOR QUESTION 1 OF HW #9 1. 16 x 8-bit Asynchronous SRAM ` define DELAY 1 module Ram (data, address, memw, memr, cs); parameter width = 8, nbytes = 16, addr = 4; input memw, memr, cs; input [addr-1:0] address; inout [width-1:0] data; reg [width-1:0] mem [nbytes-1:0]; assign #`DELAY data = (cs & memr & !memw)? mem[address]:8'bz; // change in the original code always @(posedge memw) begin if(cs) mem[address] = data; end endmodule module test; reg [3:0] address; reg memw=0; reg memr=0; reg cs=1; tri [7:0] data; integer i; reg [7:0] d; Ram r1 (data, address, memw, memr, cs); assign data = (cs && memw)? d : 8'bz; //assign data = d; initial $monitor($time,"memw=%d memr=%d data=%d add=%d",memw,memr,data,address); initial begin for(i=0;i<16;i=i+1)
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begin #2; d <= i; address <= i; memw <= 1; #2 memw <= 0; end for(i=0;i<16;i=i+1) begin //d <= 8'bz; address <= i; memr <= 1; #2 memr <= 0; end end endmodule 2. 16 x 8-bit Dual-
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271s09_HW9_Q1_Sol - SOLUTION FOR QUESTION 1 OF HW #9 1. 16...

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