EE270_HW5 - Homework 4 1. Design a fundamental mode circuit...

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Unformatted text preview: Homework 4 1. Design a fundamental mode circuit as described using NOR gates only a. It is a two input, one output device (x1,x2, z) b. When x2=1, z=0 c. The first change x1 from 0 to 1 while x2=0 cause the output z to be 1 d. The output would remain 1 until x2 goes to 1, forcing z to 0 2. Obtain a primitive flow table and a minimal‐row flow table for a fundamental asynchronous sequential network meeting the following requirements: a. There are 2 input x1, x2 and a single output b. The output is to be the same as x1 if x2=1. However if x2=0, the output is to remain fixed at its last value before x2 became 0. ...
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This note was uploaded on 02/21/2010 for the course EE 270 taught by Professor Staff during the Spring '08 term at San Jose State.

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