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# hw6_sol - ECE 442 HW6 Solutions 1 Note rst that since the...

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ECE 442 HW6 Solutions 1. Note first that, since the inverter is matched, k n = k p : k 0 n W n L n = k 0 p W p L p W p = k 0 n k 0 p L p L n W n = 180 μ 45 μ 0 . 5 μ 0 . 5 μ 0 . 75 μ = 3 μ m k n = k p = 270 μ A V 2 Also, since the magnitudes of threshold voltages for PMOS and NMOS are the same, this is a symmetric inverter, therefore: t pLH = t pHL = t p = 1 . 6 C k n V DD C = C int + C ext As derived in class: C int = C db 1 + C db 2 + 2 C gd 1 + 2 C gd 2 = ( C j · d n ) · W n +( C j · d p ) · W p + 2 C gdo · W n + 2 C gdo · W p C int = 1 f μ × 0 . 75 μ + 1 f μ × 3 μ + 2 × 0 . 4 f μ × 0 . 75 μ + 2 × 0 . 4 f μ × 3 μ = 6 . 75 fF C ext = C w + C FO C FO = C gs 1 + C gs 2 = W n L n C ox + W p L p C ox = 0 . 75 μ × 0 . 5 μ × 3 . 7 f μ 2 + 3 μ × 0 . 5 μ × 3 . 7 f μ 2 = 6 . 9375 fF C = 6 . 75 f + 2 f + 6 . 9375 f = 15 . 69 fF t pLH = t pHL = t p = 1 . 6 × 15 . 69 f 270 μ × 3 . 3 = 28 . 18 ps Now, if delay increases by 50%, the total capacitance will increase by the same ratio (since they are directly proportional to each other): Δ C = 0 . 5 × C = 7 . 85 fF 2. a) To derive the expression for V IL , we first note that NMOS is expected to be in saturation, and PMOS in the linear regime (opposite of the V IH derivation shown in class). Therefore: I DS = k n 2 ( V GSn - V tn ) 2 = k p [( V GSp - V tp ) V DSp - ( V DSp ) 2 2 ] 1

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k r 2 ( V I - V t ) 2 = ( V I - V DD + V t )( V O - V DD ) - ( V O - V DD ) 2 2 (1) Taking the partial derivative, V I , we obtain: k r 2 2 ( V I - V t ) = ( V O - V DD )+( V I - V DD + V t ) V O V I - 1 2 2 ( V O - V DD ) V O V I At the point where V I = V IL , V O
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