2x3-simul - #real_sent#exp_pkt#rcv_pkt#processed_pkt#Coded#Decoded LstReceived 156 1024 284 284 1 284 2 156 1024 284 284 3 160 1024 284 216 216 160

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(0)i0 ----- i1 (1)i4 ----- i5 (2) i2 i6 i8 | | | | | | i3 i7 i9 (3)i10 ----- i11 (4)i12 ----- i13 (5) Simulation ended after 162 cycles. CoreID #cycles #intrs(Bytes) #sent_pkt #real_sent #exp_pkt #rcv_pkt #processed_pkt #Coded #Decoded LstReceived 0 156 1024 284 284 0 0 0 0 0 0 1 0 0 0 142 0 0 0 0 0 0 2 156 1024 284 284 0 0 0 0 0 0 3 160 1024 0 0 284 283 283 141 141 161 4 0 0 0 284 0 0 0 0 0 0 5 160 1024 0 0 284 283 283 141 141 161 CoreID #cycles #intrs(Bytes) #sent_pkt
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Unformatted text preview: #real_sent #exp_pkt #rcv_pkt #processed_pkt #Coded #Decoded LstReceived 156 1024 284 284 1 284 2 156 1024 284 284 3 160 1024 284 216 216 160 4 151 5 160 1024 284 217 217 161...
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This note was uploaded on 02/24/2010 for the course ECE EE123 taught by Professor Ad during the Spring '10 term at A.T. Still University.

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2x3-simul - #real_sent#exp_pkt#rcv_pkt#processed_pkt#Coded#Decoded LstReceived 156 1024 284 284 1 284 2 156 1024 284 284 3 160 1024 284 216 216 160

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