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VHDL - Copy - EEE 333 ASU Spring 2010 David R Allee...

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EEE 333, ASU Spring 2010, David R. Allee Homework #2 solutions The objective of this homework is to exercise your learning of VHDL syntax, basic module definitions and modeling of combinational logic. You can try to use modelsim to simulate and check your answers. 1. Data Types: Chapter 2 in Ashenden’s book 1.1 Write constant declarations for the number of bits in a 32 bit word and for the number pi(3.14159). constant number_of_bits:integer:=32; constant pi:real:=3.14159; 1.2 Given the type declaration type state is (off, standby, active1, active2) what are the values of state’pos(standby) 1 state’succ(active2) error state’leftof(off) error state’val(2) active1 state’pred(active1) standby state’rightof(off) standby 1.3 For each of the following expressions, indicate whether they are syntactically correct, and if so, determine the resulting value. 2*3+6/4 7 3 + -4 error true and x and not y or z error (assume x,y,z are bit) “cat” & character’(‘0’) cat0 B”101110” sll 3 110000 (B”100010” sra 2) & X”2C” 11_1000_0010_1100 1.4 Write a counter model with a clock input
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