# HWK3 - HWK #3 Solutions Problem 3.1 a. b. A = d1+d0 -->...

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Unformatted text preview: HWK #3 Solutions Problem 3.1 a. b. A = d1+d0 --> A' = d1'd0' w = d3+d2(d1+d0) = d3+d2A (distributive) Similarly, x = d2A' + d2'(d1+d0) = d2A' + d2'A (= d2 XOR A) y = d1d0 + A' z = d0' c. To implement these expressions, use a total of eight 2-input NAND gates and 5 inverters (to compute A', d0', d1', d2', d3'). d. We have a typical speed vs. hardware tradeoff: o The circuit in part (c) uses fewer components and so would be cheaper to build. o The circuit in part (a) is a 2-level circuit (actually, 2 levels plus inverters). The circuit in part (c) is a 3-level circuit (plus inverters). So the circuit in part (a) would compute the output a little faster. e. f. Using the boolean expressions from part (b), let's fill in the truth table table. By inspection, it can be seen that the circuit outputs the binary (arithmetic) sum (wxyz) 2 = (d 3 d 2 d 1 d ) 2 PLUS 3 . The pattern holds up through d 3 d 2 d 1 d =1100; after that, we wouldn't be able to express (d 3 d 2 d 1 d ) 2 PLUS 3 with 4 bits anyway. If we look at d 3 d 2 d 1 d as a BCD digit, then we could say that wxyz is the excess-3 equivalent of d 3 d 2 d 1 d ; that is, the circuit is a BCD to excess-3 code converter . d 3 d 2 d 1 d w x y z 0 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 1 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 1 1 0 1 Problem 3.2 (a) A 2-level NOR-to-NAND circuit computes an OR function of the inputs: ((w+x)'(y+z)')' = (w+x)'' + (y+z)'' = w+x+y+z (b) To compute (a+b+c+d+e+f+g+h)': • Use 2 two-input NORs and a two-input NAND to compute a+b+c+d • Use 2 two-input NORs and a two-input NAND to compute e+f+g+h...
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## This note was uploaded on 02/26/2010 for the course ECE 290 taught by Professor Brown during the Fall '08 term at University of Illinois at Urbana–Champaign.

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HWK3 - HWK #3 Solutions Problem 3.1 a. b. A = d1+d0 -->...

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