# HWK7 - Written Hwk#7 Solution ECE 290 Problem 7.1(a CD 00...

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Written Hwk #7 Solution ECE 290 Problem Set #7 Due: October 10, 2007 Problem 7.1. (a) C D Q+ 0 0 Q 0 1 Q 1 0 0 1 1 1 This circuit has D and D' feeding into the NAND gates, so this corresponds to having S and R never equal. (b) (i) (ii) C D w x y z 0 0 1 1 y z 0 1 1 1 y z 1 0 1 0 0 1 1 1 0 1 1 0 (iii) Yes, the circuit drawn is a D latch. C is the control input and y is the state. When C = 0, then w = x = 1 and the state y persists. When C = 1: if D = 0 then w = 1 and x = 0 and the next state is y+ = 0. When C = 1: If D = 1 then w = 0 and x = 1 and the next state is y+ = 1. Problem 7.2 Consider the outputs of the D latch to be Y and Y'.

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When C = 0, the D latch is enabled and the Y and Y' are sensitive to changes in the D input where Y = D. With C = 0, the SR latch is disabled, so outputs Q and Q' are steady. When the clock goes from 0 to 1, the D latch becomes disabled after a short delay from the inverter, and outputs Y and Y' become steady. The SR latch then becomes enabled after another small delay from the second inverter. For this reason the SR latch becomes enabled shortly after the D latch is disabled. Y and Y' get transferred to Q and Q', respectively. When the clock transitions from 1 to 0, the SR latch gets disabled and the D latch
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HWK7 - Written Hwk#7 Solution ECE 290 Problem 7.1(a CD 00...

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