hwk09_f07_soln

hwk09_f07_soln - ECE 290 Fall 2007 Homework 9 Solutions 9.1...

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ECE 290 Fall 2007 Homework 9 Solutions 9.1 a. b.
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9.2 a.1. a.2.
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a.3. 1 1 1 1 1 1 Clock b. Using an asynchronous clear for the circuit implementation in part 2 above would not behave correctly. As shown in the timing diagram below, as soon as the state of 18 is reached the clear signal will go low (active) and reset the counters (after minimal delay from the signal nand gate). Because of the count of this, 18 is essentially being skipped and going from 17 to 0.
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9.3 a. b. 4 4 1 4 1
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Solution based on 74163 TI datasheet: c. Note: FF Setup time is the time for a stable transition form High to low or l ow to high. Ideal design: From 74163 datasheet (TI version on web), the input to each FF has 2 gate delays (feeding back from the output of the FF) If done for every FF of a 16-bit counter, the ideal 16-bit counter can operate at a rate of every 7 gate delays ( 2 AND gate delays for inputs + 2 delays for FF setup time + 3 delays for FF propagation) Ripple design (using circuit details from datasheet): Delay from ENT to RCO is 11 gate delays: 2 from ENT to input gates of FF 2 AND-gate delays to input 2 delays for FF setup 3 delays for FF propagation 2 from Q’ to RCO The 1 st stage has 2 gate delays from output of 1111 to RCO output. Each subsequent stage has 11 gate delays (except the last stage). Total delay is
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hwk09_f07_soln - ECE 290 Fall 2007 Homework 9 Solutions 9.1...

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