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Unformatted text preview: 2) Obtain logic hazard-free equations for the circuit. 3) Draw a gate level circuit implementation for the half adder circuit. 4) Obtain the composite Karnaugh Map for the S and R excitation inputs. 5) Obtain logic hazard-free S and R excitation input equations, and draw the half adder circuit using S-R NOR latches. 6) Draw the half adder circuit using S-R NAND latches....
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This note was uploaded on 02/27/2010 for the course ECE 620 taught by Professor Raminroosta during the Spring '10 term at CSU Northridge.
- Spring '10