hw01 - ECE420 Homework #1 10 points Using the schematic...

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ECE420 Homework #1 10 points Using the schematic Design Entry Method, design a logic circuit that has two 2- bit inputs X and Y, a 1-bit input CinOrBin, and a 1-bit control input SubAddn. When the control input SubAddn is ‘0’, the logic circuit behaves as a 2-bit adder ( X + Y + CinOrBin ) with CinOrBin as the carry-in; when the control input SubAddn is ‘1’ and the logic circuit behaves as a 2-bit subtracter ( X – Y – CinOrBin ) with CinOrBin as the borrow-in. You must use Half-Adders and Half-Subtracters as building blocks to obtain a structured design. Your design will be used to configure the target FPGA EP2C35F672C6 with the following pin assignments: Pin Assignment Table DE2 Board Componen t Names Tutorial01 Signal Names Pin Numbers SW[5] SubAddn PIN_AD13 SW[4] Y1 PIN_AF14 SW[3] Y0 PIN_AE14 SW[2] X1 PIN_P25 SW[1] X0 PIN_N26 SW[0] CinOrBin PIN_N25 LEDR[2] CoutOrBout PIN_AB21 LEDR[1] SumOrDiff1 PIN_AF23 LEDR[0]] SumOrDiff0 PIN_AE23 Block Diagram X Y CoutOrBout CinOrBin SumOrDiff SubAddn 2 2 2
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Verify your design by Functional simulation and by Timing simulation.
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This note was uploaded on 02/27/2010 for the course ECE 420 taught by Professor Georgelaw during the Spring '10 term at CSU Northridge.

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hw01 - ECE420 Homework #1 10 points Using the schematic...

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