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Unformatted text preview: SumOrDiff SubAddn 2 2 2 Level 3 (Top Design): Using full adders and full subtracters in level 2, and multiplexers to design the specified circuit Material to be submitted: 1. Top VHDL design file for Design I and Design II. Include your name in the comment header of both designs. 2. Functional simulation output that covers all possible input combinations for Design I and Design II. Manually verify that the simulation output is correct by comparing the output with the truth table values. Show manual verification work. 3. Discussion on the resource usage reported in the report file. Include comparison on resource usage with your design for homework 1. Assume both designs ( Homework 1 and Homework 2 ) use EP2C35F672C6 chip. Note : Do your own work! Select EP2C35F672C6 device....
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This note was uploaded on 02/27/2010 for the course ECE 420 taught by Professor Georgelaw during the Spring '10 term at CSU Northridge.
- Spring '10