hw02 - SumOrDiff SubAddn 2 2 2 Level 3(Top Design Using...

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ECE420 Homework #2 10 points Using the VHDL Entry Method, design a logic circuit that behaves as a 2-bit adder  ( X + Y + CinOrBin ) with carry-in when the control input SubAddn is ‘0’ and  behaves as a 2-bit subtracter ( X – Y – CinOrBin ) with borrow-in  when the control  input SubAddn is ‘1’.  Design I:     Use the Half-Adder and Half-Subtracter components declared within  the architecture. Design II:   Use the Half-Adder and Half-Subtracter components declared in a  package file located in the project folder.  Verify both designs by Functional simulation.  Design Requirements Your design must have three levels of hierarchy: Level 1 (lowest level): half adder and half subtracter. Level 2: Using half adders and half subtracters in level 1 to design full adder and full  subtracter. X Y CoutOrBout CinOrBin
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Unformatted text preview: SumOrDiff SubAddn 2 2 2 Level 3 (Top Design): Using full adders and full subtracters in level 2, and multiplexers to design the specified circuit Material to be submitted: 1. Top VHDL design file for Design I and Design II. Include your name in the comment header of both designs. 2. Functional simulation output that covers all possible input combinations for Design I and Design II. Manually verify that the simulation output is correct by comparing the output with the truth table values. Show manual verification work. 3. Discussion on the resource usage reported in the report file. Include comparison on resource usage with your design for homework 1. Assume both designs ( Homework 1 and Homework 2 ) use EP2C35F672C6 chip. Note : Do your own work! Select EP2C35F672C6 device....
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