hw03 - ECE420 Homework #3 : Design of a Counter Write VHDL...

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clk set count enable 7 ECE420 Homework #3 : Design of a Counter Write VHDL codes to model an 8-bit counter that counts every second. It counts from your last two digits of your student ID to your next two digits of your student ID. If the last two digits are greater than the next two digits, the counters counts down; otherwise, it counts up. The counter should have asynchronous set input to set the count to your last two digits of your student ID, synchronous clear input to clear the count to 0, and enable input to enable counting. Set input has higher priority than the clear input. For now, you may assume that the clock to the counter is a 1 Hz clock. For subsequent homework, you need to design a circuit that generates the 1 Hz clock signal from the 50 MHz system clock. For example: Student ID : 12345678 : Count starts from 78 down to 56, back to 78, counts down to 56, and repeat. If the counter is cleared, count starts from 0 up to 78 and then counts down to 56, back to 78, and repeat. If the counter is set, the count sets to 78. The counter will not count when it
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hw03 - ECE420 Homework #3 : Design of a Counter Write VHDL...

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