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Unformatted text preview: picture.mif and use picture.mif in the Port Map of the ROM. 3. Write the VHDL codes that meet the specified requirements. 4. Simulate the design. Work to submit 1. VHDL codes with detailed comment header and comment statements. 2. Functional Simulation output that shows the q output when the condition ( prow >=wx and prow < wx+32 and pcol >= yz and pcol < yz+32) is true and not true, and when resetn is active. Manually verify the q output with the contents of the MIF file. 3. Copy of the MIF file. Note: Because Cyclone II supports only synchronous ROM, you must configure the Altera LPM_ROM (1Kx3) as a synchronous ROM (registered input and output). 640 pixels by 480 pixels Legend: (prow, pcol) VGA monitor screen (479,0) (0,0) (479, 639) (0, 639) Block Diagram clk q resetn prow pcol 9 10 3...
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- Spring '10
- Frequency, Logic gate, Input/output, Computer display standard, XGA