hw07 - ECE420 Homework #7

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
ECE420 Homework #7 Assumption:   The frequency of the system clock is 50 MHz and the last four digits of  your student ID are wxyz. Reference:   Source code for Video Synchronization signals generation Write VHDL codes to generate the synchronization signals hsync and vsync, prow, pcol,  VGABlankn, and PixelClk  for a VGA display ( 640x480 pixel by pixel) and to display your  32x32 image at prow = wx and pcol = yz.  VGABlanks is set to Vcc (‘1’) and PixelClk is connected to Clk25MHz. Use the VHDL codes for Homework 6 as a component. Work to submit 1. VHDL codes with detailed comment header and comment statements. 2. Simulation output that covers at least two periods of scaled version of hsync signal.  Calculate the hsync period using the scale factor and the time shown. 3.
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 02/27/2010 for the course ECE 420 taught by Professor Georgelaw during the Spring '10 term at CSU Northridge.

Page1 / 3

hw07 - ECE420 Homework #7

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online