526lec6-7

# 526lec6-7 - Initial isnt Physical A B initial C = A B Then...

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2/15/2010 1 Initial isn’t Physical A B C D OUT Q 1 initial C = A & B; Then what? What happens when A or B changes? RST CLK CLR initial OUT <= 1’b0; That’s not how a flipflop works! “always” is for circuits A B C D OUT Q 2 always @(A or B) C = A & B; This is the way a gate works. RST CLK CLR always @(posedge CLK or posedge CLR) begin …. Initial Block •A n initial block starts at time 0 and runs exactly once. • Initial blocks can be used to give a variable an initial value 3 initial value. • They can also be used for setting sequences of values. • If there is more than one active statement in an initial block, keywords “begin” and “end” are needed. Begin…End • Begin…end pairs are analogous to curly braces {} in C. • A single statement does not need to be 4 A single statement does not need to be enclosed in them, two or more do. initial begin a = 1’b1; c = 1’b0; end initial rst = 1’b0; initial clk = 1’b0; Begin…End Pitfall //No begin…end needed always @(posedge CLK) if (!RST) MYREG <= 0; 5 /*Decide to add a check to see if statement was executed*/ always @(posedge CLK) begin if (!RST) MYREG <= 0; \$display (“Reset Done \n”); end Syntactically, still OK. Logically? Logically NOT OK • Second statement (display) will execute whether or not previous RST clause runs. • Display is not part of “if” clause 6 Display is not part of if clause. • No syntax error, but a logical error.

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2/15/2010 2 Use begin…end Around ‘if’ Clause always @(posedge CLK) begin if (!RST) begin Now the display is onl done if RST is 0 7 MYREG <= 0; \$display (“Reset Done”); end end only done if RST is 0. Concurrency • Verilog is used for hardware modeling. • In a circuit, many signals are changing simultaneously. 8 • A computer can typically only do one thing at a time. • Circuits are simulated by scheduling multiple events to occur at the same simulation time, but assignments are really made sequentially. Concurrency DFF1 CLK Q D DFF1 CLK Q D A B CLK2 Q 9 _ always @(posedge CLK) CLK2 <= ~CLK2; always @(posedge CLK) OUT <= A & B; Both events are concurrent. There is no way to predict which will be scheduled first. Order of statements in code is not significant. Note these devices only make sense with “always” blocks. “Initial” would be meaningless. Race Condition `timescale 1 ns / 1 ns module race (out1, out2, clk, rst); output out1, out2; input clk, rst; reg out1 out2 10 reg out1, out2; always @(posedge clk or negedge rst) if (!rst) out1 = 0; else out1 = out2; always @(posedge clk or negedge rst) if (!rst) out2 = 1; else out2 = out1; endmodule Another Race Value of B depends on order of evaluation. This order is non-deterministic. 11 always @(posedge CLK) A = A + 1; always @(posedge CLK) B = A; Order of Execution always @(posedge CLK or negedge RST) begin if (!RST) CLK2 = 1'b0; else CLK2 = ~CLK2; end always @ (posedge CLK) begin 12 if (CNT == TC && CLK2) MATCH = 1'b1; else MATCH = 1'b0; end always @(posedge CLK2 or negedge RST) begin if (!RST) CNT = 4'b0; else CNT = CNT + 1; end
2/15/2010 3 13 Output relations depend or order of execution. MATCH may go high when CNT is 15.

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526lec6-7 - Initial isnt Physical A B initial C = A B Then...

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