526lec8 - Synchronous Design Synchronous design means that all registers are clocked by the same signal Synchronous design is always desirable in

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2/18/2010 1 Synchronous Design • Synchronous design means that all registers are clocked by the same signal. • Synchronous design is always desirable in 1 Synchronous design is always desirable in digital circuits. • Not all events are synchronous. Latch Instability • Previously saw misbehaving RS latch in simulation: persistence of X values that would not happen with physical gates. • Real RS latches can misbehave too. • Simultaneous 0-0 (NAND) or 1-1 (NOR). • Timing matters. 2 RS Latch S R Q Qn 0 0 NC NC NOR A B OUT 00 1 3 0 1 0 1 1 0 1 0 1 1 X X If R and S go to 1 simultaneously, the outputs are unpredictable and may result in oscillation. 0 0 1 0 1 0 1 0 0 1 1 0 RS Latch Timing • Assume R=0, S = 1. • Outputs are stable, Q=1, Qb=0. R switches to 1 nothing else changes • R switches to 1, nothing else changes. • Q then goes to 0. Nothing else changes. • Output is 0 0. Not correct functioning of the latch, but not dangerous. 4 Simultaneous Switching • “Illegal” input condition 1-1 for NOR RS latch results in illegal output 0-0. • System is stable System is stable. • But what if both R and S switch from 0 to 1 at exactly the same time? • System becomes unstable. May oscillate. 5 Signal Arrival Times • In sequential circuits, signal arrival relationships matter. • Combinational gate: makes no difference 6 which signal arrives first. A NAND is a NAND is a NAND, no matter what the order of arrival. • Not true for register inputs. Example: DFF requires D stable before CLK.
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2/18/2010 2 DFF Made from RS Latches Before reaching final state, a change on D may have to go 7 through 2 RS latches. To have a stable state resulting from a change in D before the clock arrives, D must change before the clock. Setup Time RS latch: simultaneous arrival of inputs can cause unpredictable behavior. In order to prevent unpredictable outputs, each flipflop will have certain operating parameters 8 have certain operating parameters. One of the key parameters is setup time. This is the amount of time before the clock signal arrives that other signals need to be stable. Violation of setup times is a primary cause of malfunctioning circuits. Timing Violations 9 http://www.interfacebus.com/Design_MetaStable.html JK Flipflop NAND4 Q SD NAND2 n1 n2 10 RD CP J NAND5 Q JK_f .vsd K AND2 AND1 NOR1 NAND3 a2 a1 nr n3 Asynchronous Inputs • Clear and Preset are asynchronous in that they can change the output regardless of the clock. Their functioning however is not totally 11 • Their functioning, however, is not totally divorced from the clock. • The “release” of an asynchronous input can still interfere with the functioning of a registers if it is not coordinated with the clock. Release Violation RST CLK Violation 12 X D Q X
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2/18/2010 3 Synchronizing Reset • Reset must be able to put the circuit into a known state regardless of clock status— asynchronous assert.
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526lec8 - Synchronous Design Synchronous design means that all registers are clocked by the same signal Synchronous design is always desirable in

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