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Unformatted text preview: 2b. Implement the same function in behavioral Verilog. 3. Sketch the hardware that would result from synthesizing this code: module homework(MY_OUT, IN1, IN2, CLK); output [3:0] MY_OUT; input [3:0] IN1, IN2; input CLK; reg [3:0] MY_OUT; reg [3:0] TEMP; always @(posedge CLK) begin TEMP = IN1 + IN2; MY_OUT = TEMP + IN1; end endmodule Make your sketch at a high level of abstraction, that is, using registers and arithmetic operators rather than Boolean gates....
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- Spring '09