Week 1 Part 2

Week 1 Part 2 - EECE 201 Project Integrated Program Module 2 Week 1 Fall 2009 Set 2 Introduction to Logic Circuits Sathish Gopalakrishnan

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1 SG EECE 201, Module 2, Set 2 EECE 201 Project Integrated Program Module 2, Week 1, Fall 2009 Set 2: Introduction to Logic Circuits Sathish Gopalakrishnan Department of Electrical and Computer Engineering University of British Columbia [email protected] Office Hours (in KAIS 4045) October 28 4:00 p.m. to 5:00 p.m. October 30 9:00 a.m. to 10:00 a.m.
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2 SG EECE 201, Module 2, Set 2 Binary Variables and Functions The simplest binary element is a switch that has two states. x 1 = x 0 = (a) Two states of a switch S x (b) Symbol for a switch
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3 SG EECE 201, Module 2, Set 2 Binary Variables and Functions L(x)=x (a) Simple connection to a battery S x (b) Using a ground connection as the return path L Battery Light x Power supply S L
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4 SG EECE 201, Module 2, Set 2 Binary functions L(x 1 ,x 2 ) = x 1 .x 2 L(x 1 ,x 2 ) = x 1 + x 2 (a) The logical AND function (series connection) S x 1 L Power supply S x 2 S x 1 L Power supply S x 2 (b) The logical OR function (parallel connection) Light Light
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5 SG EECE 201, Module 2, Set 2 Binary Functions L(x 1 ,x 2 ,x 3 )=(x 1 +x 2 ).x 3 When is the light on? S x 1 L Power supply S x 2 Light S x 3
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6 SG EECE 201, Module 2, Set 2 Inversion (Complementation) S x L Power supply R Different notations for complementation:
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7 SG EECE 201, Module 2, Set 2 Truth Tables Truth tables can be used to represent binary circuits (instead of representing them with circuits and simple switches) Truth table for AND and OR functions
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8 SG EECE 201, Module 2, Set 2 Truth Tables Truth table for three-input AND and OR operations
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9 SG EECE 201, Module 2, Set 2 Basic Logic Gates x 1 x 2 x n x 1 x 2 x n + + + x 1 x 2 x 1 x 2 + x 1 x 2 x n x 1 x 2 x 1 x 2 x 1 x 2 x n (a) AND gates (b) OR gates x x (c) NOT gate
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10 SG EECE 201, Module 2, Set 2 Logic Networks Logic network or logic circuit is a circuit consisting of binary variables (inputs and outputs of the circuit) and logic gates. Example: x 1 x 2 x 3 f x 1 x 2 + ( ) x 3 =
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SG EECE 201, Module 2, Set 2 Two Basic Issues in Logic Network Design Analysis: The process of determining the function performed by an existing logic network. Synthesis: Reverse task of analysis, that is to design a network that implements a given function The analysis process is usually more straightforward and simpler than the synthesis task. For the purpose of analysis truth tables or timing diagrams
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This note was uploaded on 02/28/2010 for the course ECE 311 taught by Professor Leon during the Spring '10 term at UNBC.

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Week 1 Part 2 - EECE 201 Project Integrated Program Module 2 Week 1 Fall 2009 Set 2 Introduction to Logic Circuits Sathish Gopalakrishnan

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