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Week 2 Part 2

Week 2 Part 2 - VHDL modeling of combinational logic...

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02/11/2009 1 1 11/01/2009 EECE201 – PIP, Module 2, Wk2 VHDL modeling of combinational logic 2 11/01/2009 EECE201 – PIP, Module 2, Wk2 Why VHDL? VHDL is an international IEEE standard specification language (IEEE 1076-1993) for describing digital hardware used by industry worldwide VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language VHDL enables hardware modeling from the gate to system level VHDL provides a mechanism for digital design and reusable design documentation Extensions towards analog and mixed analog/digital modeling: VHDL-A, VHDL-AMS (IEEE standard)
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02/11/2009 2 3 11/01/2009 EECE201 – PIP, Module 2, Wk2 VHDL – goals and use Intended for: Documentation of digital systems Simulation of digital systems Synthesis of digital systems, for physical implementation (in FPGA or ASIC) Easy testing of the desired functionality at the simulation level (ASIC fabrication cost ~ $2 million! ) Comparison with visual schematic entries + more portable (IEEE standard) and text based + allows system level description in terms of generic, parameterized elements (Exm: a general n-bit adder description, in terms of behavior, not implementation) - Requires perhaps more discipline than graphical entry 4 11/01/2009 EECE201 – PIP, Module 2, Wk2 Why not VHDL? complex language – complexity inherited from Ada programming language alternative hardware or system description languages: Verilog (extensions: Verilog- A, Verilog-AMS), SystemC difficult to use for HW-SW co-design
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02/11/2009 3 5 11/01/2009 EECE201 – PIP, Module 2, Wk2 VHDL History 1981: language requirements first generated by US DoD response from need for a standardized hardware description language for the design, documentation, and verification of digital systems 1987: standardized by IEEE IEEE Std 1076-1987 recognized as American Standards Institute (ANSI) standard 1993: new improved version released IEEE Std 1076-1993 Standard package for model interoperability 9-value logic package IEEE Std 1164-1993 (STD_LOGIC_1164) 6 11/01/2009 EECE201 – PIP, Module 2, Wk2 Y Chart – representing abstraction in design Physical/Geometry Structural Behavioral Processor Hardware Modules ALUs, Registers Gates, FFs Transistors Systems Algorithms Register Transfer Logic Transfer Functions Architectural Algorithmic Functional Block Logic Circuit Rectangles Cell, Module Plans Floor Plans Clusters Physical Partitions [Gajski83] © IEEE 1983 What it does? Describe structure as interconnection of elements Binds the structure to Silicon
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02/11/2009 4 7 11/01/2009 EECE201 – PIP, Module 2, Wk2 Aspects of representation (RASSP taxonomy) 8 11/01/2009 EECE201 – PIP, Module 2, Wk2 Model levels Cells, Wire segments Transistors, Connections Transfer functions Circuit level Modules, Cells Gates, Flip- flops Boolean equations Logic level Chips, Modules Registers, Function units, Multiplexers Register transfers RT (Register transfers) level Boards, Chips Processors, Memories Algorithms, Flowcharts System level Physical description Structural description Behavior description Levels of abstraction
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