Week 3

Week 3 - 1 Module 2, Week 3 (09 November 2009), Alireza...

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Unformatted text preview: 1 Module 2, Week 3 (09 November 2009), Alireza Nojeh dopted partially from Prof. Andre Ivanov’s notes. 2 3 OTIVATION: NEED FOR MEMORY 4 5 6 7 8 9 10 11 12 13 1-BIT MEMORY ELEMENTS 14 • This is called a “Latch”: OUT is transparent to IN when clock is 1 and latches the value of IN when clock is set to 0. • How can the memory element itself be built? 15 16 17 18 1-BIT MEMORY ELEMENTS: LATCHES 19 20 Sensor SR Latch Alarm Set Reset emember the alarm system example on/off • The SR latch does exactly what we were looking for 21 his is the same as before, except that we have added a control (clock) signal. When clock = 0, the latch retains its state (the output doesn’t change) even if the S and R inputs change (because the inputs are ANDed with 0). When clock = 1, the circuit becomes like what was on the previous page nd the changes in S and R immediately affect the output. In this case (clock = 1) we say that the latch is transparent. 22 Note: we started calling the outputs Q and Q from now on (instead of Qa and Qb). Also, in the truth table we are describing what value the output will go to (Q(t+1)) when the next clock pulse comes in as a function of what was there before (Q(t)). 23 ated SR latch with NAND gates • Same truth table as the previous one • Circuit with NAND gates requires fewer transistors than the one with AND gates • Exercise: draw the timing diagram for this 24 25...
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This note was uploaded on 02/28/2010 for the course ECE 311 taught by Professor Leon during the Spring '10 term at UNBC.

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Week 3 - 1 Module 2, Week 3 (09 November 2009), Alireza...

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