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Unformatted text preview: Sequential Circuits - An Application EE 271 Lab 3 Yusuke Tsutsumi August 5, 2009 1 Abstract This report discusses the design process of both a frequency divider and a control system for the ”Trolling for Trolls” collection system. We design a frequency divider utilizing flip-flops and logic gates, on that will produce an output frequency that is 1/10th of the clock frequency. We then design a state-based redesign for a toll-bridge system meant to assist the attending troll. Following the proper design process for state-based systems, we utilize state diagrams and state tables to determine an optimal design. We also discuss implementation of the designs of the frequency divider and the collection system on a GALV10 chip and a Altera DE1 board, respectively. 2 Introduction The first part of this lab discusses the design process and implementation process of a divide-by-10 frequency divider. We are given a 2hz square wave, and our goal is to produce a 0.2hz square wave. To realize this, we utilize a series of flip-flops and logic gates toa 0....
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- Summer '09
- Frequency, Design management, Altera, Frequency divider