EE 271 Lab 3
Sequential Circuits - An Application
Using Verilog, ispLever, Quartus, the GAL 22V10, and the Altera Cyclone FPGA
University of Washington - Department of Electrical Engineering
James K. Peckol, Brigette Huang, Eddie Chan
Lab Objectives and Overview:
The purpose of this lab is to study sequential circuits, to continue to enhance our modeling
skills using the Verilog language, and to learn more about the design and development of
digital systems using sequential arrayed logics.
For this project, our goals will be to continue the design, develop, and implementation of the
trolling for tolls
Our system will be based upon two simple sequential
machines, the first will implement a timing system and the second the
trolling for tolls
collection system control logic.
Familiarity with Verilog design language, the
and development environment, the
SuperPro programmer, the GAL 22V10 gate array, the Quartus IDE, the DE1 board, and just
about everything else.
Someone’s permission to be in this class.
Nothing to do until the end
of the quarter.
Look on the class web page under documentation then find
Using ispLever Starter Software.doc,
The data sheet for the GAL 22V10 gate array,
Referenced sections from Appendices B and C in the Brown and Vranesic text, 2
The DE 1 Board tutorials on the class web page under documentation.
Cautions and Warnings…not Musings
The GAL 22V10 is a semiconductor integrated circuit. All such circuits are very
sensitive….so is your TA … treat them both nicely.
They also don’t like static discharge, so
doing so is not a good plan.
Never leave the function generator leads disconnected with the generator turned on.
signal will slowly leak out and the generator will run out of that kind of signal.
Never try to pick up stray 0’s or 1’s that may have leaked out of the function generator.
with Bill and ask to borrow a bit bucket and scoop to clean them up.
- 1 of 7 -