EE 271 Lab 1 Report

EE 271 Lab 1 Report - Lab 1 Report An Introduction to...

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Unformatted text preview: Lab 1 Report An Introduction to Modeling, Verilog, and Real World Digital Parts EE 271 AB Department of Electrical Engineering University of Washington 10 July 2009 Aryan Naraghi · Edwin Zhang Team Member Tasks Aryan Naraghi Comparator circuit implementation Multifunction circuit design and implementation Report formatting and typesetting Edwin Zhang LED circuit implementation Logic diagrams Calculations ABSTRACT Three topics were explored in this project: designing elementary digital circuits and simulating them using Verilog; implementing physical circuits based on design; and using digital IC’s to drive analog components. In exploring these topics, a sense of the importance and usefulness of Verilog was created; the idea of keeping and maintaining good documentation was reinforced; and a comprehensive, yet brief overview of digital circuits was presented. Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts TABLE OF CONTENTS Introduction Discussion Design Specifications Design Procedures Hardware Implementation Test Plan Presentation, Discussion, and Analysis of the Results Part 1 Part 2 Part 3 Error Analysis Summary and Conclusion Appendix Part 1 Inclusions Verilog code for the Comparator along with its test bench and tester (Aryan Naraghi’s Copy) Simulation Results for the Comparator (Aryan Naraghi’s Copy) Waveforms for the Comparator (Aryan Naraghi’s Copy) Verilog code for the Comparator along with its test bench and tester (Edwin Zhang’s Copy) Simulation Results for the Comparator (Edwin Zhang’s Copy) Waveforms for the Comparator (Edwin Zhang’s Copy) Simulation Results for the Comparator Without Propagation Delays Chip Report for the Comparator 4 4 4 4 5 6 7 7 9 9 10 11 12 12 12 15 16 17 20 21 22 24 Part 2 Inclusions Verilog code for MultiFunction Logic Block along with its test bench and tester 27 27 -2- Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts 29 30 31 33 Simulation results for the MultiFunction Logic Block Waveforms for the MultiFunction Logic Block Verilog Modules for the MultiFunction Logic Block and Comparator Chip Report for the MultiFunction Logic Block and the Comparator -3- Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts INTRODUCTION This project served many purposes. Altera’s Terasic DE1 development board along with its prototyping board was introduced as a tool for physically building and testing logic circuits. Verilog was introduced as a modeling tool for logic circuits and ispLEVER was introduced as a compiler for translating Verilog code into a program that an array chip can execute. This project also helped to create a solid understanding of how Verilog works, successfully combining the ideas of a test bench, simulation code, and top-level modules—not to mention how to write code that describes logic gate blocks. Finally, the idea of producing good documentation for work performed was reinforced. DISCUSSION Design Specifications Part 1 of this project consisted of implementing a simple comparator logic function onto a programmable array chip. This function took in four inputs (a, b, c, and d) and produced one output (lesseq). The output implemented the function !(!ac + !a!bd + !bcd). Part 2 of the project involved the implementation of a multifunction logic block onto the same chip that held the comparator logic function. The multifunction logic block took in four inputs (a, b, sel1, and, sel2) and produced one output (result). The truth table below (Table 1) summarizes result’s behavior. Table 1. Truth table for the multifunction logic block Inputs Output sel1 sel2 result 0 0 a and b 0 1 a or b 1 0 a xor b 1 1 0 Finally, Part 3 involved building two separate circuits in which an LED was driven using an inverter logic gate and a mechanical switch. The mechanical switch simulated the input signal to the system. In one case, closing the switch caused the LED to light up while in the other case, opening the switch caused the LED to light up. Design Procedures The Verilog code for Part 1 was provided. This code included the comparator function’s implementation along with the modules necessary for simulating its design. After fixing some minor bugs that the code had, simulations were run and the results were recorded (see -4- Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts Appendix). The code for the comparator module was then transfered to ispLEVER where it was compiled into a *.jed file for the GAL16V8 programmable gate array chip. For Part 2, a Verilog model was created for a set of specifications (as outlined in the Design Specifications section) that implemented a multifunction logic block. These specifications included a logic gate diagram, which made writing the Verilog code an easy task. Figure 1 is a reproduction of the multifunction logic gate diagram with the naming convention used in the Verilog code. Figure 1. Logic diagram for the multifunction block In addition to writing the code for the multifunction logic block, a test bench and a tester module were also written for simulation purposes. The simulation results can be found in the Appendix. After reviewing the simulation results and confirming that they matched the specifications, the multifunction module was combined with the comparator module; a top level module was also written and the resulting file was loaded in ispLEVER. ispLEVER then compiled the file into a *.jed file for the GAL16V8 programmable gate array chip. Finally, since the design procedures for the LED driver in Part 3 were given, the only thing left was its implementation. Hardware Implementation For part 1, after the *.jed file was created for the comparator module, the file was programmed onto the GAL16V8 chip using the SUPERPRO programmer. Using the chip report that was -5- Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts printed from ispLEVER (included in the Appendix), the appropriate pins were connected to the switches and LED indicator in the DE1 development board. The chip was then connected to power and ground for testing. Similar steps were taken in preparing the GAL16V8 chip for implementing Part 2. The SUPERPRO programmer was used to program the chip. The chip included both the comparator module and the multifunction module. Using the chip report from ispLEVER, all the necessary pin connections were made along with power and ground in preparation for testing. Finally, the two circuits for driving LED’s from Part 3 were built from the circuit diagrams given. Figure 2 is an illustration of how the two circuits were combined with the SN74LS04N inverter (drawn as a rectangle in the figure). Figure 2. The LED driver circuits TEST PLAN The testing procedures for Parts 1 and 2 are similar. The appropriate switches on the DE1 development board should be set to different combinations of on and off while the state of the LED’s connected to the output pin of the array chip are noted. If the on and off states of the inputs (which in this case are the switches) match the state of the output (the LED) as dictated by the design specifications, then the design can be regarded as valid. Note that only an exhaustive test of all possible combinations can verify the validity of the design. Finally, for Part 3, the test plan is to simply open and close the switches in the two circuits. In one of the circuits, the LED is driven or turned on when the switch is closed while in the other, the LED is driven when the switch is opened. -6- Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts PRESENTATION, DISCUSSION, AND ANALYSIS OF THE RESULTS Part 1 After testing the comparator circuit, it was determine that the circuit met the requirements of the specifications. What follows is the responses to the questions posed in the project handout. 1. Figure 3 is the logic diagram for the comparator circuit. Figure 3. Logic diagram for the comparator 2. Below is the truth table for the circuit. This true table represents the behavior of ideal circuit elements. As such, some variation exists between the simulation results and this truth table. Table 2. Truth table for the comparator circuit Output d lesseq = !(!ac + !a!bd + !bcd) 0 1 1 0 0 0 1 0 0 1 1 1 0 0 1 0 0 1 -7- Inputs a 0 0 0 0 0 0 0 0 1 b 0 0 0 0 1 1 1 1 0 c 0 0 1 1 0 0 1 1 0 Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts Inputs a 1 1 1 1 1 1 1 b 0 0 0 1 1 1 1 c 0 1 1 0 0 1 1 Table Table 2. Truth table for the comparator circuit Output d lesseq = !(!ac + !a!bd + !bcd) 1 1 0 1 1 0 0 1 1 1 0 1 1 1 3. The output of the Verilog program does not agree with the truth table (Table 2). This is because the Verilog program includes propagation delays which delay the time it takes different input signals to propagate through the circuit and reach the output. Thus, the output of a given set of inputs is not necessarily correct because that output could easily be the output from a previous set of input signals. 4. The error in the output that appears after the “Producing Glitch” message is a result of the delay in the circuit. This error does not occur when all the delays are removed from the Verilog code (i.e., setting delay = 0). 5. The output log with delay = 0 is noticeably different from that of the original code with delay = 10. The output of the new Verilog program agrees with the truth table (Table 2). The most noticeable difference is the fact that the first entry is no longer null. The overall pattern is also different, reflecting the lack of delay in the digital signals passing through the gates. 6. Changing stimDelay to 5 time units reduces the time between each simulation, so the time intervals displayed on the output log are three times shorter than the original since the original stimDelay was 15 time units. 7. The spikes happen because with delay = 0, any pulses that are caused by delays should have width of zero, but the computer cannot properly model this zero width. The spikes can be removed by making sure that all paths from all given inputs pass through the same number of gates. For those paths that do not pass through the same number of gates, adding a buffer anywhere along the way will ensure its time synchronization with the other paths. Figure 4 on the next page is a modified circuit diagram with the buffers added in. -8- Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts Figure 4. Logic diagram for the comparator with buffers 8. There are many advantages to using a program like Verilog. Verilog is supported by most organizations that offer digital hardware technology. This means that Verilog can be implemented in a wide variety of chips without changing the Verilog specifications. Another advantage is that Verilog code can facilitate hierarchal design thanks to its modular approach. Finally, Verilog source code is plain text which not only complements its portability, but also allows for easy sharing between collaborators. Part 2 After implementing the multifunction circuit on the same programmable array chip as the comparator circuit and comparing the different input and output combinations against the specifications, it was determined that the multifunction implementation met all specifications and was thus valid. Part 3 For the first circuit in part 3, with the switch closed, the voltage across the 10 Ω resistor was 1.96 mV and the current through it was 0.196 mA. The voltage across the 330 Ω resistor was 0.85 V and the current through it was 2.56 mA. Finally, V1 was 4.35 V. For the second circuit, with the switch open, the voltage across the 1.0 KΩ resistor was 1.00 mV and the current through it was 1.00 nA. The voltage across the 330 Ω was 2.55 V and the current through it was 7.73 mA. V2 was 0.161 V. Table 3 summarizes the current values. -9- Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts Table Table 3. Circuit measurements Parameter Value |I1| 0.196 mA |I2| 2.56 mA |I3| 1.00 nA |I4| 7.73 mA |V1| 4.35 V |V2| 0.161 V Table 4 displays selected data from the SN74LS04N inverter data sheet. Table 4. SN74LS04N parameters from its data sheet Description Value Type of Value Low-level input current -0.4 mA Maximum High level output current -0.4 mA Maximum High-level input current 20 µA Maximum Low-level output current 8 mA Maximum High-level output voltage 3.24 V Typical Low-level output voltage 0.25 V Typical Parameter IIL IOH IIH IOL VOH VOL For the currents, these values are the maximum currents that can either enter or leave the inverter (the signs depend on whether the current is entering or leaving the inverter). The voltages are the typical voltages that are associated with high or low logic levels. By analyzing the data, it becomes clear that I1 is IIL; I2 is IOH; I3 is IIH; and I4 is IOL. It is important to keep in mind that the values for the currents given in the data sheet are maximums and that the currents given in Table 3 are magnitudes. Finally, V1 is VOH and V2 is VOL. The data sheet values given for VOH and VOL are typical values, so the measured values certainly fall within range. By looking at both LED’s directly while they were on, it was difficult to determine which was brighter. Theoretically, however, the LED in the second configuration should be brighter. This is because the voltage drop across the 330 Ω and the LED in the second configuration (given by 5 V - V2) is higher than that in the first configuration (given by 5 V - V1). ERROR ANALYSIS The biggest source of error in this project would likely be the inability to distinguish the brightness of the LED’s. This is due to many factors such as little variability between the amount of light each LED produced and the fact that the environment (the Department of Electrical - 10 - Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts Engineering’s lab) is very high-lit. Despite this, a theoretical distinction was made to determine which LED was brighter. Finally, a logic high was not exactly 5 V, but integrated circuits are built with tolerance, so this was not an issue. SUMMARY AND CONCLUSION This project involved three major components: designing elementary digital circuits and simulating them in Verilog; implementing physical circuits based on design; and using digital IC’s to drive analog components. The design portion introduced Verilog as a tool for writing code to describe digital logic circuits as well as writing simulation code. It also served as a glimpse of problems with real-world parts. The project also exposed Altera’s Terasic DE1 development board as well as IC’s as implementation tools. Finally, the idea of manipulating analog parts using digital parts was introduced. The material presented in this project was new and rather alien as compared to previous work in classes such as EE 215. This illustrates many of the differences between analog and digital circuits. Despite the differences, it was interesting to see the two used in conjunction with one another. The use of software to simulate hardware before implementation also proved to be a powerful method. This project took over 30 man hours to complete, longer than anticipated, which suggests that getting a quality product out takes effort and a lot of hard work. - 11 - Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts APPENDIX Part 1 Inclusions Verilog code for the Comparator along with its test bench and tester (Aryan Naraghi’s Copy) /************************************************************** * Title: Pre-Lab 1: Sample Verilog source code A Simple Comparator * Model type: Gate level * Description: This Verilog source code simulates all input conditions of a lesseq than comparison * Programmer: Aryan Naraghi * Date: 06/26/2009 **************************************************************/ // text after a '//' on a line is considered a comment // multiple line comments are enclosed by '/*' and '*/' /************************************************************** * Define the test bench module. **************************************************************/ module testBench; // wires connect things together wire lesseq, a, b, c, d; Comparator myComp (lesseq, a, b, c, d); TestModule myTester (a,b,c,d, lesseq); endmodule /************************************************************** * Define the Comparator module. **************************************************************/ module Comparator(lesseq, a, b, c, d); // within the modules, wires are implied…we can put them in if we want to parameter delay = 10; output lesseq; // Ouputs: lesseq input a, b, c, d; // Inputs: to compare, ab and cd // This is a structural model // We're building a gate level model... with propagation delay // YOU DO NOT HAVE TO TYPE THESE COMMENT LINES. // Gate instantiation format: // name-of-module #(prop. delay) assigned-name (outputs-list, inputs_list) and #delay and1(term0, notC, notD); and #delay and2(term1, a,b); and #delay and3(term2, a, c, notD); and #delay and4(term3, b, notC); and #delay and5(term4, a, notC); not inv0(notC, c); not inv1(notD,d); - 12 - Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts or or1(lesseq, term0, term1, term2, term3, term4); endmodule //close Comparator module /************************************************************** * Define the tester module. **************************************************************/ module TestModule (a,b,c,d, lesseq); // declare test module // Declare variables: input lesseq; // Module inputs output a, b, c, d; // Module outputs parameter stimDelay = 15; // Delay between generating stimuli reg a, b, c, d; // regs for setting values for checking outputs // a variable must be of type reg in order to // assign a value to it initial // this initial block assigns initializing begin // values to the designated variables a = 0; b = 0; c = 0; d = 0; end // run the simulation // this block of code is run one time initial // this initial block will apply the test vectors begin // begin initial loop // * obtain graphical waveform output of signals // * '$display("…"), simply displays the text that is between quotes to the screen. // * '$monitor("…",..,..)' displays the variables stated to // * the right of the quotes-using the format specified between the quotes. // * Formats for . '$display and $monitor... // * %b - binary digit output format // * \t - tab (default: 5 spaces) // * $time - Verilog's automatic time keeper variable // output states of signals to screen // display the results in an output log $display("CLOCK\t\t INPUTS \t\t OUTPUT\t\tTIME"); $display("--a-- \t --b--\t --c--\t--d--\t --lesseq--\t\t------"); $monitor(" %b \t %b \t %b \t %b \t\t %b" ,a,b,c,d,lesseq,$time); // The following is our test code or test vectors. // begin a second block to perform the simulation - 13 - Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts repeat (2) // repeat this process twice for illustration begin // begin REPEAT loop // we write in decimal #stimDelay {a,b,c,d} = #stimDelay {a,b,c,d} = #stimDelay {a,b,c,d} = #stimDelay {a,b,c,d} = #stimDelay #stimDelay #stimDelay #stimDelay #stimDelay #stimDelay #stimDelay #stimDelay #stimDelay #stimDelay #stimDelay #stimDelay {a,b,c,d} {a,b,c,d} {a,b,c,d} {a,b,c,d} {a,b,c,d} {a,b,c,d} {a,b,c,d} {a,b,c,d} {a,b,c,d} {a,b,c,d} {a,b,c,d} {a,b,c,d} = = = = = = = = = = = = and the compiler translates to binary 0; // a=0, b=0, c=0, 1; // a=0, b=0, c=0, 2; // a=0, b=0, c=1, 3; // a=0, b=0, c=1, 4; 5; 6; 7; // // // // a=0, a=0, a=0, a=0, b=1, b=1, b=1, b=1, c=0, c=0, c=1, c=1, d=0 d=1 d=0 d=1 d=0 d=1 d=0 d=1 8; // a=1, b=0, c=0, d=0 9; // a=1, b=0, c=0, d=1 10; // a=1, b=0, c=1, d=0 11; // a=1, b=0, c=1, d=1 12; // a=1, b=1, c=0, d=0 13; // a=1, b=1, c=0, d=1 14; // a=1, b=1, c=1, d=0 15; // a=1, b=1, c=1, d=1 end // close the REPEAT loop // the following code illustrates how we can test for aberrant conditions // we use the specific SEQUENCE of events to cause a glitch - were there others begin $display("Producing Glitch"); #stimDelay {a,b,c,d} = 0; // a=0, b=0, c=0, d=0 #stimDelay {a,b,c,d} = 10; // a=1, b=0, c=1, d=0 end #(2*stimDelay); // simulation $stop; simulation interactive mode or '$finish;' $finish; needed to see END of // temporarily stops // goto Verilog // need to type 1.1 // finish simulation end // close second initial loop endmodule // close test-module - 14 - Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts Simulation Results for the Comparator (Aryan Naraghi’s Copy) Log File Generated : 07/09/9 Working directory: F:\EE271\Labs\Lab1\Part1\Lab1\ Executable file: C:\SynaptiCAD\bin\simxgen.exe Program arguments: C:\SynaptiCAD\bin\simxgen.exe +libext+.v+.vo +linedebug --scd_dbgsymbols --scd_nosim +timescale+1ns/1ps +incdir+./ -y lib/verilog/ -y lib/ comparitor0.v SynaptiCAD VHDL/Verilog simulator rev. 37857.10470. vlog_l: Warning 34004 ./comparitor0.v(31,42): Extended ASCII character seen. vlog_p: Note: Preprocessing... vlog_p: Note: comparitor0.v vlog_a: Note: Analyzing... vlog_a: Note: comparitor0.v vlog_a: Note: Parsing success. 0 error(s), 1 warning(s) vlog_c: Note: Compiling... vlog_c: Note: comparitor0.v vlog_c: Note: Compilation success. 0 error(s), 0 warning(s) elab: Note: Elaborating... elab: Note: Top-level "testBench". elab: Note: Elaborate success. 0 error(s), 0 warning(s) codegen: Note: Generating code... cpp_c: Note: C/C++ compilation started using: MS Visual C++ compiler. cpp_c: Note: C/C++ compilation success. simgen: Note: Simulator generate success. 0 error(s), 1 warning(s) Process exited with code 0. Working directory: F:\EE271\Labs\Lab1\Part1\Lab1\ Executable file: F:\EE271\Labs\Lab1\Part1\Lab1\simxsim.exe Program arguments: F:\EE271\Labs\Lab1\Part1\Lab1\simxsim.exe -s +loadpli1=syncadverilogx.dll SynaptiCAD VHDL/Verilog simulator rev. 37849.10461 vpi_r: Note: PLI veriusertfs array loaded from library: `syncadverilogx.dll' using bootstrap: `register_syncad_tasks' Init time: 0.0 s (CPU time: 0.0 s) sim> start_corba_msg_pump sim> run SIM: CLOCK INPUTS OUTPUT TIME SIM: --a-- --b-- --c-- --d-- --lesseq-- -----SIM: 0 0 0 0 x 0 SIM: 0 0 0 0 1 10 SIM: 0 0 0 1 1 30 SIM: 0 0 0 1 0 40 SIM: 0 0 1 0 0 45 SIM: 0 0 1 1 0 60 SIM: 0 1 0 0 0 75 SIM: 0 1 0 0 1 85 SIM: 0 1 0 1 1 90 SIM: 0 1 1 0 1 105 SIM: 0 1 1 0 0 115 SIM: 0 1 1 1 0 120 SIM: 1 0 0 0 0 135 SIM: 1 0 0 0 1 145 SIM: 1 0 0 1 1 150 SIM: 1 0 1 0 1 165 SIM: 1 0 1 1 1 180 SIM: 1 0 1 1 0 190 SIM: 1 1 0 0 0 195 SIM: 1 1 0 0 1 205 - 15 - Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts SIM: 1 1 0 SIM: 1 1 1 SIM: 1 1 1 SIM: 0 0 0 SIM: 0 0 0 SIM: 0 0 0 SIM: 0 0 1 SIM: 0 0 1 SIM: 0 1 0 SIM: 0 1 0 SIM: 0 1 0 SIM: 0 1 1 SIM: 0 1 1 SIM: 0 1 1 SIM: 1 0 0 SIM: 1 0 0 SIM: 1 0 0 SIM: 1 0 1 SIM: 1 0 1 SIM: 1 0 1 SIM: 1 1 0 SIM: 1 1 0 SIM: 1 1 0 SIM: 1 1 1 SIM: Producing Glitch SIM: 1 1 1 SIM: 0 0 0 SIM: 1 0 1 Simulation stopped via $stop(1) at sim> 1 0 1 0 1 1 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 0 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 1 1 1 210 225 240 255 270 280 285 300 315 325 330 345 355 360 375 385 390 405 420 430 435 445 450 465 1 1 480 0 1 495 0 1 510 time 540 ns Waveforms for the Comparator (Aryan Naraghi’s Copy) - 16 - Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts Verilog code for the Comparator along with its test bench and tester (Edwin Zhang’s Copy) /************************************************************** * Title: Pre-Lab 1: Sample Verilog source code A Simple Comparator * Model type: Gate level * Description: This Verilog source code simulates all input conditions of a lesseq than comparison * Programmer: Edwin Zhang * Date: Date typed **************************************************************/ // text after a '//' on a line is considered a comment // multiple line comments are enclosed by '/*' and '*/' /************************************************************** * Define the test bench module. **************************************************************/ module testBench; // wires connect things together wire lesseq, a, b, c, d; Comparator myComp (lesseq, a, b, c, d); TestModule myTester (a, b, c, d, lesseq); endmodule /************************************************************** * Define the Comparator module. **************************************************************/ module Comparator(lesseq, a,b,c,d); // within the modules, wires are implied…we can put them in if we want to parameter delay = 10; output lesseq; // Outputs: lesseq input a, b, c, d; // Inputs: to compare, ab and cd // Gate instantiation format: // name-of-module #(prop. delay) assigned-name (outputs-list, inputs_list) and and and and and #delay #delay #delay #delay #delay and1(term0, and2(term1, and3(term2, and4(term3, and5(term4, notC, notD); a,b); a, c, notD); b, notC); a, notC); not #delay inv0(notC, c); not #delay inv1(notD,d); or #delay or1(lesseq, term0, term1, term2, term3, term4); endmodule //close Comparator module /************************************************************** * Define the tester module. **************************************************************/ - 17 - Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts module TestModule (a,b,c,d, lesseq); // declare test module // Declare variables: input lesseq; // Module inputs output a, b, c, d; // Module outputs parameter stimDelay = 15; // Delay between generating stimuli reg a, b, c, d; // regs for setting values for checking outputs // a variable must be of type reg in order to // assign a value to it initial // this initial block assigns initializing begin // values to the designated variables a = 0; b = 0; c = 0; d = 0; end // run the simulation // this block of code is run one time initial // this initial block will apply the test vectors begin // begin initial loop // * obtain graphical waveform output of signals // * '$display("…"), simply displays the text that is between quotes to the screen. // * '$monitor("…",..,..)' displays the variables stated to // * the right of the quotes-using the format specified between the quotes. // * Formats for . '$display and $monitor... // * %b - binary digit output format // * \t - tab (default: 5 spaces) // * $time - Verilog's automatic time keeper variable // output states of signals to screen // display the results in an output log $display("CLOCK\t\t INPUTS \t\t OUTPUT\t\tTIME"); $display("--a-- \t --b--\t --c--\t--d--\t --lesseq--\t\t------"); $monitor(" %b \t %b \t %b \t %b \t\t %b" ,a,b,c,d,lesseq,$time); // The following is our test code or test vectors. // begin a second block to perform the simulation repeat (2) // repeat this process twice for illustration begin // begin REPEAT loop // we write in decimal and the compiler translates to binary #stimDelay {a,b,c,d} = 0; // a=0, b=0, c=0, d=0 #stimDelay {a,b,c,d} = 1; // a=0, b=0, c=0, d=1 - 18 - Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts #stimDelay {a,b,c,d} = 2; // a=0, b=0, c=1, d=0 #stimDelay {a,b,c,d} = 3; // a=0, b=0, c=1, d=1 #stimDelay #stimDelay #stimDelay #stimDelay #stimDelay #stimDelay #stimDelay #stimDelay #stimDelay #stimDelay #stimDelay #stimDelay {a,b,c,d} {a,b,c,d} {a,b,c,d} {a,b,c,d} {a,b,c,d} {a,b,c,d} {a,b,c,d} {a,b,c,d} {a,b,c,d} {a,b,c,d} {a,b,c,d} {a,b,c,d} = = = = = = = = = = = = 4; 5; 6; 7; // // // // a=0, a=0, a=0, a=0, b=1, b=1, b=1, b=1, c=0, c=0, c=1, c=1, d=0 d=1 d=0 d=1 8; // a=1, b=0, c=0, d=0 9; // a=1, b=0, c=0, d=1 10; // a=1, b=0, c=1, d=0 11; // a=1, b=0, c=1, d=1 12; // a=1, b=1, c=0, d=0 13; // a=1, b=1, c=0, d=1 14; // a=1, b=1, c=1, d=0 15; // a=1, b=1, c=1, d=1 end // close the REPEAT loop // the following code illustrates how we can test for aberrant conditions // we use the specific SEQUENCE of events to cause a glitch - were there others begin $display("Producing Glitch"); #stimDelay {a,b,c,d} = 0; // a=0, b=0, c=0, d=0 #stimDelay {a,b,c,d} = 10; // a=1, b=0, c=1, d=0 end #(2*stimDelay); // needed to see END of simulation //$stop; // temporarily stops simulation // goto Verilog interactive mode // need to type 1.1 or '$finish;' $finish; // finish simulation end // close second initial loop endmodule // close test-module - 19 - Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts Simulation Results for the Comparator (Edwin Zhang’s Copy) Log File Generated : 07/09/9 Working directory: F:\EE271\Labs\Lab1\Part1\blarg\ Executable file: C:\SynaptiCAD\bin\simxgen.exe Program arguments: C:\SynaptiCAD\bin\simxgen.exe +libext+.v+.vo +linedebug --scd_dbgsymbols --scd_nosim +timescale+1ns/1ps +incdir+./ -y lib/verilog/ -y lib/ honk.v SynaptiCAD VHDL/Verilog simulator rev. 37857.10470. vlog_l: Warning 34004 ./honk.v(31,42): Extended ASCII character seen. vlog_p: Note: Preprocessing... vlog_p: Note: honk.v vlog_a: Note: Analyzing... vlog_a: Note: honk.v vlog_a: Note: Parsing success. 0 error(s), 1 warning(s) vlog_c: Note: Compiling... vlog_c: Note: honk.v vlog_c: Note: Compilation success. 0 error(s), 0 warning(s) elab: Note: Elaborating... elab: Note: Top-level "testBench". elab: Note: Elaborate success. 0 error(s), 0 warning(s) codegen: Note: Generating code... cpp_c: Note: C/C++ compilation started using: MS Visual C++ compiler. cpp_c: Note: C/C++ compilation success. simgen: Note: Simulator generate success. 0 error(s), 1 warning(s) Process exited with code 0. Working directory: F:\EE271\Labs\Lab1\Part1\blarg\ Executable file: F:\EE271\Labs\Lab1\Part1\blarg\simxsim.exe Program arguments: F:\EE271\Labs\Lab1\Part1\blarg\simxsim.exe -s +loadpli1=syncadverilogx.dll SynaptiCAD VHDL/Verilog simulator rev. 37849.10461 vpi_r: Note: PLI veriusertfs array loaded from library: `syncadverilogx.dll' using bootstrap: `register_syncad_tasks' Init time: 0.0 s (CPU time: 0.0 s) sim> start_corba_msg_pump sim> run SIM: CLOCK INPUTS OUTPUT TIME SIM: --a-- --b-- --c-- --d-- --lesseq-- -----SIM: 0 0 0 0 x 0 SIM: 0 0 0 1 1 30 SIM: 0 0 1 0 1 45 SIM: 0 0 1 1 0 60 SIM: 0 1 0 0 0 75 SIM: 0 1 0 1 0 90 SIM: 0 1 1 0 1 105 SIM: 0 1 1 1 1 120 SIM: 1 0 0 0 0 135 SIM: 1 0 0 1 0 150 SIM: 1 0 1 0 1 165 SIM: 1 0 1 1 1 180 SIM: 1 1 0 0 1 195 SIM: 1 1 0 1 1 210 SIM: 1 1 1 0 1 225 - 20 - Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts SIM: SIM: SIM: SIM: 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 1 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 1 1 1 1 1 0 1 240 255 270 275 285 300 315 330 345 360 375 390 405 420 435 450 465 480 495 510 515 525 SIM: 0 0 1 0 SIM: 0 0 1 1 SIM: 0 1 0 0 SIM: 0 1 0 1 SIM: 0 1 1 0 SIM: 0 1 1 1 SIM: 1 0 0 0 SIM: 1 0 0 1 SIM: 1 0 1 0 SIM: 1 0 1 1 SIM: 1 1 0 0 SIM: 1 1 0 1 SIM: 1 1 1 0 SIM: Producing Glitch SIM: 1 1 1 1 SIM: 0 0 0 0 SIM: 1 0 1 0 SIM: 1 0 1 0 SIM: 1 0 1 0 Simulation finished via $finish(1) at time 540 ns Simulation time: 0.2 s (CPU time: 0.2 s) sim> start_corba_msg_pump sim> exit Waveforms for the Comparator (Edwin Zhang’s Copy) - 21 - Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts Simulation Results for the Comparator Without Propagation Delays Log File Generated : 07/09/9 Working directory: F:\EE271\Labs\Lab1\Part1\Lab1\ Executable file: C:\SynaptiCAD\bin\simxgen.exe Program arguments: C:\SynaptiCAD\bin\simxgen.exe +libext+.v+.vo +linedebug --scd_dbgsymbols --scd_nosim +timescale+1ns/1ps +incdir+./ -y lib/verilog/ -y lib/ comparitor0.v SynaptiCAD VHDL/Verilog simulator rev. 37857.10470. vlog_l: Warning 34004 ./comparitor0.v(31,42): Extended ASCII character seen. vlog_p: Note: Preprocessing... vlog_p: Note: comparitor0.v vlog_a: Note: Analyzing... vlog_a: Note: comparitor0.v vlog_a: Note: Parsing success. 0 error(s), 1 warning(s) vlog_c: Note: Compiling... vlog_c: Note: comparitor0.v vlog_c: Note: Compilation success. 0 error(s), 0 warning(s) elab: Note: Elaborating... elab: Note: Top-level "testBench". elab: Note: Elaborate success. 0 error(s), 0 warning(s) codegen: Note: Generating code... cpp_c: Note: C/C++ compilation started using: MS Visual C++ compiler. cpp_c: Note: C/C++ compilation success. simgen: Note: Simulator generate success. 0 error(s), 1 warning(s) Process exited with code 0. Working directory: F:\EE271\Labs\Lab1\Part1\Lab1\ Executable file: F:\EE271\Labs\Lab1\Part1\Lab1\simxsim.exe Program arguments: F:\EE271\Labs\Lab1\Part1\Lab1\simxsim.exe -s +loadpli1=syncadverilogx.dll SynaptiCAD VHDL/Verilog simulator rev. 37849.10461 vpi_r: Note: PLI veriusertfs array loaded from library: `syncadverilogx.dll' using bootstrap: `register_syncad_tasks' Init time: 0.0 s (CPU time: 0.0 s) sim> start_corba_msg_pump sim> run SIM: CLOCK INPUTS OUTPUT TIME SIM: --a-- --b-- --c-- --d-- --lesseq-- -----SIM: 0 0 0 0 1 0 SIM: 0 0 0 1 0 30 SIM: 0 0 1 0 0 45 SIM: 0 0 1 1 0 60 SIM: 0 1 0 0 1 75 SIM: 0 1 0 1 1 90 SIM: 0 1 1 0 0 105 SIM: 0 1 1 1 0 120 SIM: 1 0 0 0 1 135 SIM: 1 0 0 1 1 150 SIM: 1 0 1 0 1 165 SIM: 1 0 1 1 0 180 SIM: 1 1 0 0 1 195 SIM: 1 1 0 1 1 210 SIM: 1 1 1 0 1 225 SIM: 1 1 1 1 1 240 SIM: 0 0 0 0 1 255 SIM: 0 0 0 1 0 270 SIM: 0 0 1 0 0 285 SIM: 0 0 1 1 0 300 - 22 - Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts SIM: 0 1 0 SIM: 0 1 0 SIM: 0 1 1 SIM: 0 1 1 SIM: 1 0 0 SIM: 1 0 0 SIM: 1 0 1 SIM: 1 0 1 SIM: 1 1 0 SIM: 1 1 0 SIM: 1 1 1 SIM: Producing Glitch SIM: 1 1 1 SIM: 0 0 0 SIM: 1 0 1 Simulation stopped via $stop(1) at sim> 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 1 0 1 1 1 315 330 345 360 375 390 405 420 435 450 465 1 1 480 0 1 495 0 1 510 time 540 ns - 23 - Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts Chip Report for the Comparator Page 1 ispLEVER 6.0.00.34.28.06 - Device Utilization Chart Fri Jun 26 16:49:24 2009 -------------------------------------------------------------------------------Module : 'comparator' -------------------------------------------------------------------------------Input files: ABEL PLA file : comparitor0.tt3 Device library : P16V8AS.dev Output files: Report file : comparitor0.rpt Programmer load file : comparitor0.jed -------------------------------------------------------------------------------- Page 2 ispLEVER 6.0.00.34.28.06 - Device Utilization Chart Fri Jun 26 16:49:24 2009 P16V8AS Programmed Logic: -------------------------------------------------------------------------------- lesseq = !( !a & c # !a & !b & d # !b & c & d ); Page 3 ispLEVER 6.0.00.34.28.06 - Device Utilization Chart Fri Jun 26 16:49:24 2009 P16V8AS Chip Diagram: -------------------------------------------------------------------------------- P16V8AS a b c +---------\ /---------+ | \ / | | ----- | | 1 20 | Vcc | | | 2 19 | | | | 3 18 | - 24 - Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts d GND | | | 4 17 | | | | 5 16 | !lesseq | | | 6 15 | | | | 7 14 | | | | 8 13 | | | | 9 12 | | | | 10 11 | | | | | `---------------------------' SIGNATURE: N/A Page 4 ispLEVER 6.0.00.34.28.06 - Device Utilization Chart Fri Jun 26 16:49:24 2009 P16V8AS Resource Allocations: -------------------------------------------------------------------------------- Device | Resource | Design | Resources | Available | Requirement | Unused ======================|===========|=============|============== | | | Input Pins: | | | | | | Input: | 10 | 4 | 6 ( 60 %) | | | Output Pins: | | | | | | In/Out: | 6 | 0 | 6 (100 %) Output: | 2 | 1 | 1 ( 50 %) | | | Buried Nodes: | | | | | | Input Reg: | - | - | Pin Reg: | - | - | Buried Reg: | - | - | - Page 5 ispLEVER 6.0.00.34.28.06 - Device Utilization Chart Fri Jun 26 16:49:24 2009 P16V8AS Product Terms Distribution: -------------------------------------------------------------------------------- Signal | Pin | Terms | Terms | Terms - 25 - Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts Name | Assigned | Used | Max | Unused =========================================|==========|=======|=======|======= lesseq | 16 | 3 | 8 | 5 ==== List of Inputs/Feedbacks ==== Signal Name | Pin | Pin Type =========================================|==========|========= a | 1 | INPUT b | 2 | INPUT c | 3 | INPUT d | 4 | INPUT Page 6 ispLEVER 6.0.00.34.28.06 - Device Utilization Chart Fri Jun 26 16:49:24 2009 P16V8AS Unused Resources: -------------------------------------------------------------------------------- Pin | Pin | Product | Flip-flop Number | Type | Terms | Type =======|========|=============|========== 5 | INPUT | - | - 6 | INPUT | - | - 7 | INPUT | - | - 8 | INPUT | - | - 9 | INPUT | - | - 11 | INPUT | - | - 12 | BIDIR | NORMAL 8 | - 13 | BIDIR | NORMAL 8 | - 14 | BIDIR | NORMAL 8 | - 15 | OUTPUT | NORMAL 8 | - 17 | BIDIR | NORMAL 8 | - 18 | BIDIR | NORMAL 8 | - 19 | BIDIR | NORMAL 8 | - - 26 - Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts Part 2 Inclusions Verilog code for MultiFunction Logic Block along with its test bench and tester /***************************************** * Programmers: Aryan Naraghi & Edwin Zhang * Date: 07/02/09 * Description: This program implements the specifications mentioned in Part 2 of lab 1. This is a multifunction logic block. *****************************************/ // Define the test bench module. module testBench; wire result, sel1, sel2, a, b; MultiFunction myMultiFunction(result, sel1, sel2, a, b); TestModule myTester(sel1, sel2, a, b, result); endmodule // Define the multifunction logic block's module. module MultiFunction(result, sel1, sel2, a, b); output result; // Output: result input sel1, sel2, a, b; // INPUTS: sel1, sel2, a, b // Gate assignments and and0(and0Output, and and1(and1Output, and and2(and2Output, and and3(and3Output, a, b); notSel1, and0Output, notSel2); notSel1, orOutput, sel2); sel1, xorOutput, notSel2); or or0(orOutput, a, b); xor xor0(xorOutput, a, b); not not1(notSel1, sel1); not not2(notSel2, sel2); or(result, and1Output, and2Output, and3Output); endmodule // Define the tester module. module TestModule(sel1, sel2, a, b, result); input result; // Module inputs output sel1, sel2, a, b; // Module outputs integer i; // Intialize this variable for the for loop later parameter stimDelay = 15; // Delay between stimuli reg sel1, sel2, a, b; // Allow the assignment of values to these variables initial // Initialize designated variables begin sel1 = 0; sel2 = 0; a = 0; b = 0; end - 27 - Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts initial begin // The template for how the simulation data should be displayed $display("=======INPUTS======== =OUTPUT= ============TIME============"); $display("sel1 sel2 a b result"); $monitor(" %b %b %b %b %b%d", sel1, sel2, a, b, result, $time); repeat(2)// Repeat the process twice begin // Run the simulation 16 times. for(i = 0; i < 16; i = i + 1) begin // i will assume decimal values from 0 to 15. // The compiler will convert them into binary // For example, i = 8 will correspond to sel1 = 1, // sel2 = a = b = 0 since 8 (decimal) corresponds to // 1000 (binary). #stimDelay{sel1, sel2, a, b} = i; end // Close for loop end // Close the repition #(2*stimDelay); $stop; $finish; end endmodule - 28 - Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts Simulation results for the MultiFunction Logic Block Log File Generated : 07/03/9 Working directory: F:\EE271\Labs\Lab1\Part2\MultiFunction\ Executable file: C:\SynaptiCAD\bin\simxgen.exe Program arguments: C:\SynaptiCAD\bin\simxgen.exe +libext+.v+.vo +linedebug --scd_dbgsymbols --scd_nosim +timescale+1ns/1ps +incdir+./ -y lib/verilog/ -y lib/ multifunction.v SynaptiCAD VHDL/Verilog simulator rev. 37857.10470. vlog_p: Note: Preprocessing... vlog_p: Note: multifunction.v vlog_a: Note: Analyzing... vlog_a: Note: multifunction.v vlog_a: Note: Parsing success. 0 error(s), 0 warning(s) vlog_c: Note: Compiling... vlog_c: Note: multifunction.v vlog_c: Note: Compilation success. 0 error(s), 0 warning(s) elab: Note: Elaborating... elab: Note: Top-level "testBench". elab: Note: Elaborate success. 0 error(s), 0 warning(s) codegen: Note: Generating code... cpp_c: Note: C/C++ compilation started using: MS Visual C++ compiler. cpp_c: Note: C/C++ compilation success. simgen: Note: Simulator generate success. 0 error(s), 0 warning(s) Process exited with code 0. Working directory: F:\EE271\Labs\Lab1\Part2\MultiFunction\ Executable file: F:\EE271\Labs\Lab1\Part2\MultiFunction\simxsim.exe Program arguments: F:\EE271\Labs\Lab1\Part2\MultiFunction\simxsim.exe -s +loadpli1=syncadverilogx.dll SynaptiCAD VHDL/Verilog simulator rev. 37849.10461 vpi_r: Note: PLI veriusertfs array loaded from library: `syncadverilogx.dll' using bootstrap: `register_syncad_tasks' Init time: 0.0 s (CPU time: 0.0 s) sim> start_corba_msg_pump sim> run SIM: =======INPUTS======== =OUTPUT= ============TIME============ SIM: sel1 sel2 a b result SIM: 0 0 0 0 0 0 SIM: 0 0 0 1 0 30 SIM: 0 0 1 0 0 45 SIM: 0 0 1 1 1 60 SIM: 0 1 0 0 0 75 SIM: 0 1 0 1 1 90 SIM: 0 1 1 0 1 105 SIM: 0 1 1 1 1 120 SIM: 1 0 0 0 0 135 SIM: 1 0 0 1 1 150 SIM: 1 0 1 0 1 165 SIM: 1 0 1 1 0 180 SIM: 1 1 0 0 0 195 SIM: 1 1 0 1 0 210 SIM: 1 1 1 0 0 225 SIM: 1 1 1 1 0 240 SIM: 0 0 0 0 0 255 SIM: 0 0 0 1 0 270 SIM: 0 0 1 0 0 285 SIM: 0 0 1 1 1 300 SIM: 0 1 0 0 0 315 - 29 - Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts SIM: 0 1 0 1 1 330 SIM: 0 1 1 0 1 345 SIM: 0 1 1 1 1 360 SIM: 1 0 0 0 0 375 SIM: 1 0 0 1 1 390 SIM: 1 0 1 0 1 405 SIM: 1 0 1 1 0 420 SIM: 1 1 0 0 0 435 SIM: 1 1 0 1 0 450 SIM: 1 1 1 0 0 465 SIM: 1 1 1 1 0 480 Simulation stopped via $stop(1) at time 510 ns sim> run Simulation finished via $finish(1) at time 510 ns Simulation time: 0.3 s (CPU time: 0.3 s) sim> start_corba_msg_pump sim> exit Process exited with code 0. Waveforms for the MultiFunction Logic Block - 30 - Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts Verilog Modules for the MultiFunction Logic Block and Comparator /***************************************** * Programmer: Aryan Naraghi & Edwin Zhang * Date: 07/02/09 * Description: This program combines the implementation of the Comparator and the MultiFunction logic blocks. (Lab 1, parts 1 and 2) *****************************************/ module MyTopModule(lesseq, result, comparatorA, comparatorB, comparatorC, comparatorD, sel1, sel2, a, b); output lesseq, result; input comparatorA, comparatorB, comparatorC, comparatorD, sel1, sel2, a, b; Comparator myComparator(lesseq, comparatorA, comparatorB, comparatorC, comparatorD); MultiFunction myMultiFunction(result, sel1, sel2, a, b); endmodule // Define the comparator's module. module Comparator(lesseq, a, b, c, d); output lesseq; // Ouput: lesseq input a, b, c, d; // Inputs: a, b, c, d and and1(term0, notC, notD); and and2(term1, a, b); and and3(term2, a, c, notD); and and4(term3, b, notC); and and5(term4, a, notC); not inv0(notC, c); not inv1(notD, d); or or1(lesseq, term0, term1, term2, term3, term4); endmodule // Define the multifunction logic block's module. module MultiFunction(result, sel1, sel2, a, b); output result; // Output: result input sel1, sel2, a, b; // INPUTS: sel1, sel2, a, b // Gate assignments and and0(and0Output, and and1(and1Output, and and2(and2Output, and and3(and3Output, a, b); notSel1, and0Output, notSel2); notSel1, orOutput, sel2); sel1, xorOutput, notSel2); or or0(orOutput, a, b); xor xor0(xorOutput, a, b); not not1(notSel1, sel1); - 31 - Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts not not2(notSel2, sel2); or(result, and1Output, and2Output, and3Output); endmodule - 32 - Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts Chip Report for the MultiFunction Logic Block and the Comparator Page 1 ispLEVER 6.0.00.34.28.06 - Device Utilization Chart Thu Jul 02 15:07:12 2009 -------------------------------------------------------------------------------Module : 'mytopmodule' -------------------------------------------------------------------------------Input files: ABEL PLA file : final.tt3 Device library : P16V8AS.dev Output files: Report file : final.rpt Programmer load file : final.jed -------------------------------------------------------------------------------- Page 2 ispLEVER 6.0.00.34.28.06 - Device Utilization Chart Thu Jul 02 15:07:12 2009 P16V8AS Programmed Logic: -------------------------------------------------------------------------------- lesseq = !( !comparatorA & comparatorC # !comparatorA & !comparatorB & comparatorD # !comparatorB & comparatorC & comparatorD ); result = !( sel1 & sel2 # !sel1 & !sel2 & !a # sel1 & a & b # !sel1 & !sel2 & !b # !a & !b ); Page 3 ispLEVER 6.0.00.34.28.06 - Device Utilization Chart Thu Jul 02 15:07:12 2009 P16V8AS Chip Diagram: -------------------------------------------------------------------------------- P16V8AS +---------\ /---------+ | \ / | - 33 - Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts comparatorA comparatorB comparatorC comparatorD sel1 sel2 a b GND | ----- | | 1 20 | Vcc | | | 2 19 | | | | 3 18 | | | | 4 17 | | | | 5 16 | !result | | | 6 15 | !lesseq | | | 7 14 | | | | 8 13 | | | | 9 12 | | | | 10 11 | | | | | `---------------------------' SIGNATURE: N/A Page 4 ispLEVER 6.0.00.34.28.06 - Device Utilization Chart Thu Jul 02 15:07:12 2009 P16V8AS Resource Allocations: -------------------------------------------------------------------------------- Device | Resource | Design | Resources | Available | Requirement | Unused ======================|===========|=============|============== | | | Input Pins: | | | | | | Input: | 10 | 8 | 2 ( 20 %) | | | Output Pins: | | | | | | In/Out: | 6 | 0 | 6 (100 %) Output: | 2 | 2 | 0 ( 0 %) | | | Buried Nodes: | | | | | | Input Reg: | - | - | Pin Reg: | - | - | Buried Reg: | - | - | - Page 5 ispLEVER 6.0.00.34.28.06 - Device Utilization Chart Thu Jul 02 15:07:12 2009 - 34 - Naraghi, Zhang An Introduction to Modeling, Verilog, and Real World Digital Parts P16V8AS Product Terms Distribution: -------------------------------------------------------------------------------- Signal | Pin | Terms | Terms | Terms Name | Assigned | Used | Max | Unused =========================================|==========|=======|=======|======= lesseq | 15 | 3 | 8 | 5 result | 16 | 5 | 8 | 3 ==== List of Inputs/Feedbacks ==== Signal Name | Pin | Pin Type =========================================|==========|========= comparatorA | 1 | INPUT comparatorB | 2 | INPUT comparatorC | 3 | INPUT comparatorD | 4 | INPUT sel1 | 5 | INPUT sel2 | 6 | INPUT a | 7 | INPUT b | 8 | INPUT Page 6 ispLEVER 6.0.00.34.28.06 - Device Utilization Chart Thu Jul 02 15:07:12 2009 P16V8AS Unused Resources: -------------------------------------------------------------------------------- Pin | Pin | Product | Flip-flop Number | Type | Terms | Type =======|========|=============|========== 9 | INPUT | - | - 11 | INPUT | - | - 12 | BIDIR | NORMAL 8 | - 13 | BIDIR | NORMAL 8 | - 14 | BIDIR | NORMAL 8 | - 17 | BIDIR | NORMAL 8 | - 18 | BIDIR | NORMAL 8 | - 19 | BIDIR | NORMAL 8 | - - 35 - ...
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