p73-colohan - Optimistic Intra-Transaction Parallelism on...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Optimistic Intra-Transaction Parallelism on Chip Multiprocessors Christopher B. Colohan ? , Anastassia Ailamaki ? , J. Gregory Steffan † , and Todd C. Mowry ? ‡ ? School of Computer Science Carnegie Mellon University Pittsburgh, PA 15213 USA { colohan,natassa,tcm } @cs.cmu.edu † Department of Electrical & Computer Engineering University of Toronto Toronto, Ontario M5S 3G4 Canada [email protected] ‡ Intel Research Pittsburgh 4720 Forbes Ave., Suite 410 Pittsburgh, PA 15213 USA [email protected] Abstract With the advent of chip multiprocessors, ex- ploiting intra-transaction parallelism is an at- tractive way of improving transaction perfor- mance. However, exploiting intra-transaction parallelism in existing database systems is difficult, for two reasons: first, significant changes are required to avoid races or con- flicts within the DBMS, and second, adding threads to transactions requires a high level of sophistication from transaction program- mers. In this paper we show how dividing a transaction into speculative threads solves both problems—it minimizes the changes re- quired to the DBMS, and the details of par- allelization are hidden from the transaction programmer. Our technique requires a lim- ited number of small, localized changes to a subset of the low-level data structures in the DBMS. Through this method of parallelizing transactions we can dramatically improve per- formance: on a simulated 4-processor chip- multiprocessor, we improve the response time by 36–74% for three of the five TPC-C trans- actions. 1 Introduction We are in the midst of a revolution in microprocessor design: computer systems from all of the major man- Permission to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct commercial advantage, the VLDB copyright notice and the title of the publication and its date appear, and notice is given that copying is by permission of the Very Large Data Base Endowment. To copy otherwise, or to republish, requires a fee and/or special permission from the Endowment. Proceedings of the 31st VLDB Conference, Trondheim, Norway, 2005 ufacturers that feature chip multiprocessors (CMPs) and simultaneous multithreading (SMT) are entering the marketplace. Examples include Intel’s “Smith- field” (dual-core Pentium IV’s with 2-way SMT), IBM’s Power 5 (combinable, dual-core, 2-way SMT processors), AMD’s Opteron (dual-core), and Sun Microsystems’s Niagara (an 8-processor CMP). How can database systems exploit this increasing abun- dance of hardware-supported threads? Currently, for OLTP workloads, threads are primarily used to in- crease transaction throughput ; ideally, we could also use these parallel resources to decrease transaction la- tency . Although most commercial database systems do exploit intra-query parallelism within a transaction, this form of parallelism is only useful for long running queries, while OLTP workloads tend to issue multiple...
View Full Document

This note was uploaded on 03/01/2010 for the course ICT ... taught by Professor ... during the Three '10 term at University of Sydney.

Page1 / 12

p73-colohan - Optimistic Intra-Transaction Parallelism on...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online