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Unformatted text preview: S. If your name has fewer than three letters, be inventive. Let the propagation delay of the gate be 10 ns. Using the I/O panel, cycle your program through 00, 01, 11, 10 a couple of times, and use the LW Select All, copy and paste commands to copy the resulting Timing Panel and your complete VHDL code into your assignment. 8) (4) Write a VHDL program to simulate a one-bit adder. Use the first two letters of your last name to label the addends (i.e., the bits to be added), and include your last name in the name of the circuit. A full adder has three inputs: the two bits to be added, and carry_in. It has two outputs: sum and carry_out. Include your VHDL code in your assignment. Toggle the I/O panel buttons until sum=0 and carry_out=1, and use PrtSc to include a copy of the timing display showing all your variables and your VHDL code. TA: Max Points Q1 2 Q2 2 Q3 3 Q4 4 Q5 2 Q6 4 Q7 4 Q8 4 TOTAL 25...
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This note was uploaded on 03/03/2010 for the course ECSE 2610 taught by Professor Ji during the Spring '08 term at Rensselaer Polytechnic Institute.
- Spring '08