EL 6183 Week No 2 - Polytechnic University EL 6183 EE 4163...

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Polytechnic University EL 6183 EE 4163 DSP lab Lab #2 Input-Output with the DSK A) Objectives At the end of this lab, students will Learn about the features of the TLVAIC23 Stereo Codec used in the TMS320C6713 board. Write C/C++ Codes using the CCS Integrated Development Environment (IDE). Know how to input data to and output data from the C671X processor. Learn how to write interrupt driven and polling driven programs. 1
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Learn how to generate sinusoidal signals analytically, or by using an array of sine samples or using a difference equation. Learn how to write a slider GEL file to vary parameters without stopping the processor. Plot signals in the time domain and in the frequency domain using the CCS Graph feature B) Lab Report For lab report #2, in addition to: the traditional well formatted cover page, the signed pages of this lab, the conclusion, students are expected to: write down the steps necessary to launch any CCS feature, include a screen capture of every single feature learned in this lab, insert their C/C++ source codes, explain the choices made if any, etc. C) The TLV320AIC23B Stereo Codec on the TMS 320C6713 DSK board 2
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The TLV320AIC23B Stereo Codec is used on the TMS320C6713 board. The TLV320AIC23B is a high-performance stereo audio codec with integrated analog functionality. The analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) within the TLV320AIC23B use multibit sigma-delta technology with integrated oversampling digital interpolation filters. Data-transfer word lengths of 16, 20, 24, and 32 bits, with sample rates from 8 kHz to 96 kHz, are supported. Integrated analog features consist of stereo-line inputs with an analog bypass path, a stereo headphone amplifier, with analog volume control and mute, and a complete electret-microphone-capsule biasing and buffering solution. The headphone amplifier is capable of delivering 30 mW per channel into 32 Ω. The analog bypass path allows use of the stereo-line inputs and the headphone amplifier with analog volume control, while completely bypassing the codec, thus enabling further design flexibility, such as integrated FM tuners. A microphone bias-voltage output provides a low-noise current source for electret-capsule biasing. The AIC23B has an integrated adjustable microphone amplifier (gain adjustable from 1 to 5) and a programmable gain microphone amplifier (0 dB or 20 dB). The microphone signal can be mixed with the output signals if a sidetone is required. 3
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1. Features 1.42 V – 3.6 V Core Digital Supply: Compatible With TI C54x DSP Core Voltages 2.7 V – 3.6 V Buffer and Analog Supply: Compatible Both TI C54x DSP Buffer Voltages 8-kHz – 96-kHz Sampling-Frequency Support 16/20/24/32-Bit Word Lengths Stereo-Line Inputs and Stereo-Line Outputs 2. Functional Block 4
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AIC 23 B Functional Block 3. Operating frequency The codec has a 12MHz system clock. The 12MHz system clock corresponds to USB
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This note was uploaded on 03/04/2010 for the course EE ee taught by Professor Ee during the Spring '10 term at Istanbul Technical University.

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EL 6183 Week No 2 - Polytechnic University EL 6183 EE 4163...

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